Fast recovery PNP loaded bipolar static RAM memory cell with an independent current path

A high speed bipolar memory for being interfaced with bit lines for reading data thereto and writing data therefrom comprising:

• first and second sense nodes;
• first and second NPN bipolar transistors each associated with one of said first and second sense nodes and having the collector thereof connected to the associated one of said sense nodes and the base thereof connected to the other of said sense nodes;
• a current source connected between the emitters of said first and second NPN transistors and a first reference voltage;
• first and second PNP load transistors associated with said first and second sense nodes, respectively, and connected between the associated one of said sense nodes and a second reference voltage higher than said first reference voltage with each of said PNP transistors having the base thereof connected to said associated sense node, the collector thereof connected to the opposite one of said sense nodes and the emitter thereof connected to said second reference voltage;
• write means associated with one of said first and second sense nodes for interfacing the associated one of said first and second sense nodes with the bit lines and selectively providing a current path from an external reference supply to said associated sense node in response to data on the interfaced bit line to change the logic state of the memory cell by injecting current into the collector of the PNP transistor associated with the sense node to aid in pulling the associated sense node from a lower voltage to a higher voltage;
• and
• read means for interfacing a selected one of said first and second sense nodes with the bit lines to enable sensing of the logic state in the memory cell.

A high speed memory cell comprising:

• first and second sense nodes;
• a first reference voltage node for being disposed at a first predetermined reference voltage;
• a holding current node for providing a current sink;
• first and second cross-coupled pairs of PNP and NPN transistors associated with said first and second sense nodes respectively, and disposed between said first reference voltage node and said holding current node, said first and second cross-coupled transistor pairs each operating in a saturated or a nonsaturated state and opposite each other, said saturated and nonsaturated states corresponding to a high or low logic state, respectively;
• write circuitry for selectively providing an independent current path from an external reference voltage to said first and second sense node to change the state of the associated one of said first and second pairs from a saturated to a nonsaturated state when externally generated data is to be written to the memory cell that requires the logic state of the memory cell to be changed;
• and
• read means for sensing the logic state of the memory cell.

A bipolar semiconductor memory utilizing ECL technology, comprising:

• an array of memory cells arranged in rows and columns for storing first and second logic states;
• a plurality of row lines, each associated with one of said rows of memory cells;
• a current source associated with each row of memory cells for providing a holding current to each of said memory cells in said associated row;
• a plurality of column lines associated with each of the columns, said column lines comprised of write column lines and read column lines;
• each of said memory cells comprising:
• first and second sense nodes,
• first and second pairs of PNP and NPN transistors associated with said first and second sense nodes, respectively, and arranged in a cross-coupled configuration, each of said first and second pairs connected between said row lines and said associated current source and each of said first and second pairs alternating between a saturated state and a nonsaturated state corresponding to said first and second logic states,
• write means for interfacing between said first and second sense nodes and said associated write column line to selectively provide a current path to said associated sense nodes to force said associated pair from the saturated state to the nonsaturated state to allow the logic state in said memory cell to be altered, and
• read means for selectively interfacing the logic state stored in said first and second sense nodes with said read column lines;
• address means for receiving and decoding an external address and generating a column select signal associated with select ones of said columns of memory cells and a row select signal associated with select ones of said rows of memory cells;
• word line drive means for receiving said row select signal and selecting the corresponding one of said rows of memory cells through the associated one of said row lines;
• read circuitry for sensing the logic state of the select memory cells interfaced with said selected read column lines corresponding to said select signals and outputting data therefrom;
• and
• write circuitry for receiving input data and interfacing said received input data with said write column lines for the select column and row and controlling said write means in said selected memory cells to interface with an external supply through said write column lines to cause current flow to a select one of said first and second sense nodes through said current path to cause said associated first and second pairs to go from a saturated to an unsaturated state.