US 4,855,903 AGranted

Topologically-distributed-memory multiprocessor computer

AssigneeState University of New York

InventorsHerbert R. Carleton, Jeremy Q. Broughton

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Abstract

A modular, expandable, topologically-distributed-memory multiprocessor computer comprises a plurality of non-directly communicating slave processors under the control of a synchronizer and a master processor. Memory space is partitioned into a plurality of memory cells. Dynamic variables may be mapped into the memory cells so that they depend upon processing in nearby partitions. Each slave processor is connected in a topologically well-defined way through a dynamic bi-directional switching system (gateway) to different respective ones of the memory cells. Access by the slave processors to their respective topologically similar memory cells occurs concurrently or in parallel in such a way that no data-flow conflicts occur. The topology of data distribution may be chosen to take advantage of symmetries which occur in broad classes of problems. The system may be tied to a host computer used for data storage and analysis of data not efficiently processed by the multiprocessor computer.

Claims45

Dependent claims

A multiprocessor computer, comprising:

a grid-like network of processors and memory cells, said processors and memory cells defining the nodes of said grid and being logically configured in an alternating sequence within said grid, such that individual processors are logically interposed between surrounding memory cells and individual memory cells are logically interposed between surrounding processors;
communication means for providing direct, parallel communications between the individual processors and their logically surrounding memory cells and between the individual memory cells and their logically surrounding processors, such that nearest adjacent processors articulate at least two common memory cells and nearest adjacent memory cells are articulated by at lest two common processors;
switching means provided logically between the individual processors and each of their surrounding memory cells and between the individual memory cells and each of their surrounding processors, and cooperating with said communications means, for enabling/disabling communication between each individual processor and a particular one of it surrounding memory cells and between each individual memory cell and a particular one of its surrounding processors;
and
synchronizing means, cooperating with said switching means, for synchronizing the switching of communications between the individual processors and particular ones of their surrounding memory cells, and between the individual memory cells and particular ones of their surrounding processors.

2 more elements

A multiprocessor computer, comprising:

a plurality of processors;
first means, connected to each of said processors for providing parallel communications to and from each of said processors;
a data memory space comprising a plurality of memory cells;
second means, connected to each of said memory cells, for providing parallel communications to and from each of said memory cells;
means, connected between said first means and said second means, for switchably connecting each processor to a plurality of logically adjacent ones of said memory cells, each processor being associated with a different plurality of memory cells, each such plurality comprising a different subset of the set of the memory cells comprising said memory space, logically neighboring processors being thereby associated with logically neighboring memory cells in an overlapping manner, each of said memory cells being thereby switchably associated with a plurality of said processors which is a different plurality than is associated with a logically neighboring memory cell;
synchronizing means in communication with said switchably connecting means for synchronizing the switching of connections between processors and memory cells, such that, simultaneously, each of said processors is connected, in parallel, to a topologically similar one of it respectively associated memory cells;
and
means cooperating with said synchronizing means for alternating said parallel connections between said processors and different, topologically similar ones of their respectively associated memory cells.

5 more elements

In a computer system comprising a plurality of processors, a data memory space further comprising a plurality of memory cells, communications means linking each processor to a different subset of the set of memory cells comprising said data memory space, the members of each of said subsets being logically neighboring memory cells, and switching means cooperating with said communications means for enabling/disabling communications between each processor and a particular one of its associated memory cells, a method of electronic computation comprising the steps of:

(a) causing said switching means to provide non-conflicting access between each processor and a topologically-similar one of their respectively associated memory cells;
(b) processing, in parallel, data within each of said topologically-similar memory cells using the respectively accessing processor;
(c) causing said switching means to synchronously switch access for each of said processors to a non-conflicting, topologically-similar memory cell other than the cell most recently accessed thereby;
(d) processing, in parallel, data from said topologically-similar memory cells using the currently respectively accessing ones of said plurality of processors;
and
(e) repeating steps (c) and (d) until a pre-determined condition is satisfied.

3 more elements

A multiprocessor computer, comprising:

a plurality of slave processors;
first means, coupled to each of said slave processors, for providing communications to and from said slave processors;
a data memory space partitioned into a plurality of memory cells;
second means, coupled to each of said memory cells, for providing communications to and from said memory cells;
gateway means, coupled between said first and second means, for switchably associating individual ones of said slave processors each with a different plurality of ones of said memory cells such that individual ones of said memory cells are likewise switchably associated each with a different plurality of individual ones of said slave processors;
synchronizing means, coupled to said gateway means, for synchronizing direct parallel connections between said slave processors and their respectively associated memory cells;
and
a master processor, in communication with said slave processors and said synchronizing means, for supervising the operation of said slave processors and said synchronizing means, said master processor being adapted to cause said synchronizing means to synchronize connections in said gateway means in phases in such a manner as to switchably connect the individual ones of said slave processors respectively each to a particular one of a first set of topologically similar ones of their respectively associated memory cells during a first phase and to a different particular one of a second set of topologically similar ones of their respectively associated memory cells during a second phase.

5 more elements

A multiprocessor computer, comprising:

a plurality of slave processors;
first means, coupled to each of said slave processors, for providing communications to and from said slave processors;
a data memory space partitioned into a plurality of memory cells;
second means, coupled to each of said memory cells, for providing communications to and from said memory cells;
gateway means, coupled between said first and second means, for switchably associating individual ones of said slave processors each with a different plurality of ones of said memory cells such that individual ones of said memory cells are likewise switchably associated each with a different plurality of individual ones of said slave processors;
synchronizing means, coupled to said gateway means, for synchronizing direct concurrent connections between said slave processors and their respectively associated memory cells;
and
a master processor, in communication with said slave processors and said synchronizing means, for supervising the operation of said slave processors and said synchronizing means, said master processor being adapted to cause said synchronizing means to synchronize connections in said gateway means in phases in such a manner as to switchably connect the individual ones of said slave processors respectively each to a particular one of a first set of topologically similar ones of their respectively associated memory cells during a first phase and to different particular one of a second set of topologically similar ones of their respectively associated memory cells during a second phase

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/147,595Filed 22 Jan 1988 · continuation
Priority: 20 Dec 1984
Granted: 8 Aug 1989
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 13/1657
In a multiprocessor architecture: access to multiple memories
G06F 15/17343
Direct connection machines, e.g. completely connected computers, point to point communication networks: wherein the interconnection is dynamically…
G06F 15/80
Architectures of general purpose stored program computers: comprising an array of processing units with common control, e.g. single instruction…
G06F
Computing and data processing