Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate

A method for the manufacture of an integrated semiconductor circuit containing a bipolar transistor and complementary n-channel and p-channel MOS transistors which comprises:

• (a) providing a p-doped semiconductor substrate,
• (b) providing a double insulating layer of silicon oxide and silicon nitride over said substrate,
• (c) structuring said silicon nitride layer to define areas in which collector terminals are to be formed,
• (d) implanting n-doping ions into said areas,
• (e) removing the silicon nitride in those areas of said substrate in which n-wells are to be formed,
• (f) implanting n-doping ions into the areas in which n-wells are to be formed,
• (g) diffusing said n-doping ions to form said n-wells while simultaneously oxidizing the surface of the n-well areas,
• (h) implanting boron ions to form a surface distal region of a channel zone of the said n-channel transistors, using the oxide surfaces produced in step (g) as a mask,
• (i) applying a double layer of silicon oxide and silicon nitride after removing the previously grown oxide,
• (j) implanting boron ions into the desired field oxide regions of said n-channel transistors,
• (k) locally oxidizing the field oxide regions utilizing the previously deposited silicon nitride as an oxidation mask,
• (l) oxidizing the surface to generate gate oxides,
• (m) boron-doping the channel regions of the n-channel and p-channel transistors,
• (n) boron-doping the base zone of the bipolar transistor,
• (o) removing the gate oxide in the region of said base zone,
• (p) depositing at least a single layer of a metal silicide over the surface,
• (q) depositing a surface-wide oxide layer over said surface,
• (r) implanting arsenic ions through said surface,
• (s) structuring the metal silicide layer of step (p) for the manufacture of the gate electrodes of the n-channel and p-channel transistors and the emitter terminals of the bipolar transistors,
• (t) generating the emitter zone of said bipolar transistors by high temperature treatment,
• (u) depositing a surface-wide silicon oxide layer by vapor phase deposition on the surface,
• (v) simultaneously forming the source/drain regions of the n-channel transistors and the n.sup.+ collector contact the bipolar transistor by phosphorus ion implantation,
• (w) simultaneously forming the source/drain regions of the p-channel transistor and the p.sup.+ base contact of the bipolar transistors by boron ion implantation, and
• (x) applying terminal electrodes to the resulting transistor structures.