Gain scaling of oversampled analog-to-digital converters

An A/D converter front end quantizer having an analog input voltage node and having specified maximum values for positive and negative analog input voltages, comprising:

• a. a first switched capacitor accumulator comprising:
• i. a first switched capacitor for sampling the analog input voltage, said first switched capacitor being selectively connectable to the analog input voltage node or to a charge summing node of said first stage;
• ii. a second switched capacitor for sampling a positive voltage reference, said second switched capacitor being selectively connectable to a positive voltage reference or to said summing node, the magnitude of said positive voltage reference being greater than the magnitude of the specified maximum positive analog input voltage divided by the ratio of capacitance of said second switched capacitor to said first switched capacitor;
• iii. a third switched capacitor for sampling a negative voltage reference, said third switched capacitor being selectively connectable to a negative voltage reference or o said charge summing node, the magnitude of said negative voltage reference being greater than the magnitude of the specified maximum negative analog input voltage divided by the ratio of capacitance of said third switched capacitor to said first switched capacitor;
• iv. In integrator having an input coupled to said charge summing node, the output of said integrator providing an output of said first stage;
• b. a second switched capacitor accumulator having an output node and having an input coupled to the output of said first switched capacitor accumulator;
• c. a clocked comparator having an output node and having an input coupled to the output node of said second switched capacitor accumulator;
• d. circuit means coupled to the output node of said clocked comparator and responsive to the output signal thereon for selectively generating control signals for controlling the switching of said first, second, and third switched capacitors.

A method for selectively applying charge to a charge summing node, said charge being received from either a positive reference voltage or from a negative reference voltage, said method comprising:

• a. coupling a first switched capacitor between the positive reference voltage and ground while coupling a second switched capacitor between the negative reference voltage and ground to thereby charge said first switched capacitor from the positive reference voltage while simultaneously charging said second switched capacitor from the negative reference voltage;
• then,
• b. uncoupling said first switched capacitor from said positive reference voltage and simultaneously uncoupling said second switched capacitor from said negative reference voltage;
• and then,
• c. coupling said first switched capacitor between ground and said charge summing node and discharging said second switched capacitor to ground if it is desired to apply charge to the charge summing node from the positive reference voltage, or, alternatively, coupling said second switched capacitor between ground and said charge summing node and discharging said first switched capacitor to ground if it is desired to apply charge to the charge summing node from the negative reference voltage.