Semiconductor memory device

A semiconductor memory device of a redundancy configuration having lines of main memory cells each storing data of one bit and a line of spare memory cells each storing data of one bit, the spare line being formed to substitute a defective line containing a defective main memory cell if there is such a defective line, the substitution by the spare line being achieved by having an arrangement by which the spare line is selected by the address of the defective line, in substitution for the defective line, said semiconductor memory device comprising:

• a comparator for comparing an input address received by the memory device, with an address of the defective line which has been programmed in said comparator;
• a spare line selector responsive to the output of the comparator for selecting the spare line when the input address is found to coincide with the programmed address;
• a line decoder responsive to the input address for selecting one of the lines of the main memory cells;
• means responsive to the output of the comparator for producing a signal for inactivating the line decoder when the input address is found to coincide with the programmed address;
• means for applying the input address to the line decoder and to the comparator so that said comparator receives said input address a predetermined time period before said line decoder receives said input address;
• and
• wherein said comparator comprises a dynamic NOR gate having discharge paths each formed of a gate element receiving a bit of the input address or an inversion of said bit to be opened or closed depending on the value of the particular bit of the input address currently applied, and PROM elements each being connected in series with the gate element, the PROM elements of the discharge paths being programmed to represent an address of a defective line, the dynamic NOR gate having a first node forming an output thereof and a second node, each of the series connections of the PROM element and the gate element being connected across the first and the second nodes, and equalizing means for causing the potential on the second node to be substantially identical with the potential on the first node during a precharge period.

A semiconductor memory device of a redundancy configuration having lines of main memory cells each storing data of one bit and a line of spare memory cells each storing data of one bit, the spare line being formed to substitute a defective line containing a defective main memory cell if there is such a defective line, the substitution by the spare line being achieved by having an arrangement by which the spare line is selected by the address of the defective line in substitution for the defective line, said semiconductor memory device comprising:

• a comparator comparing an input address received by the memory device with an address of the defective line which has been programmed in said comparator;
• a spare line selector responsive to the output of the comparator for selecting the spare line when the input address is found to coincide with the programmed address;
• a line decoder responsive to the input address for selecting one of the lines of the main memory cells;
• means responsive to the output of the comparator for producing a signal for inactivating the line decoder when the input address is found to coincide with the programmed address;
• means for applying the input address to the line decoder and to the comparator so that said comparator receives said input address a predetermined time period before said line decoder receives said input address;
• and
• means for precharging the output of the comparator during a precharge period.