Timing recovery scheme for burst communication systems

In a circuit for receiving a bit stream in a burst mode communication system wherein the bit stream has a preamble portion and a data portion, a timing recovery apparatus adapted to provide a clock signal having the proper phase and frequency for sampling each bit of the data portion of the bit stream, the timing recovery apparatus comprising:

• frequency reference means, for outputting a reference signal;
• oscillator means, responsive to a first control signal, for producing an oscillator output signal having a frequency determined by the first control signal,
• said oscillator means further having an injection input, the oscillator output signal being phase aligned with a signal applied to the injection input;
• divider means, responsive to the oscillator output signal from said oscillator means, for producing the clock signal, the clock signal having a frequency equal to or sub-harmonically related to the oscillator output signal;
• phase detector means, responsive to the oscillator output signal from said oscillator means and the reference signal from said frequency reference means, for producing a relative phase signal indicating the relative phase between the reference signal and the oscillator output signal;
• filter means, responsive to the relative phase signal from said phase detector means, for producing a filtered signal;
• sample-and-hold means, responsive to the filtered signal from said filter means, for producing the first control signal, and for selectively sampling and holding the filtered signal;
• storage means, fed by said sample-and-hold means, for storing the amplitude of the first control signal and for producing a second control signal, the second control signal having substantially the same amplitude as the stored amplitude of the first control signal;
• subtracting means, fed by said sample-and-hold means and said storage means, for subtracting the first control signal from the second control signal to form an error signal;
• comparison means, fed by said subtracting means, for indicating when the error signal exceeds predetermined limits;
• detector means, arranged to receive the preamble portion of the bit stream, for providing a signal indicating the data rate of the data portions of the bit stream;
• and
• coupling means, coupled to said detection means and said oscillator means, for coupling the signal indicating the data rate to the injection input of said oscillator means during the preamble portion of the bit stream.

An apparatus responsive to a clock sequence contained in a bit stream, said bit stream additionally including a second sequence following said clock sequence, said apparatus providing a clock signal during said second sequence of said bit stream, said clock signal maintaining a substantially fixed phase and frequency relationship with said clock sequence, said apparatus comprising:

• a phase lock loop including
• a voltage-controlled oscillator having an injection input, for providing said clock signal,
• a local frequency reference for generating a reference signal, and
• phase detector means for providing a control signal to said oscillator indicative of the phase relationship between said clock signal and said reference signal;
• means for injecting said clock sequence into said oscillator for aligning the phase of said clock signal with the phase of said clock sequence;
• and
• means for maintaining said clock signal at substantially the phase of said clock sequence during said second sequence.

Apparatus for providing a clock signal having a predetermined phase and frequency relationship with respect to a received signal, said received signal comprising a preamble portion and a data portion, said apparatus comprising:

• a phase lock loop including
• a voltage-controlled oscillator having an injection input, for providing said clock signal,
• a local frequency reference for generating a reference signal, and
• phase detector means for providing a control signal to said oscillator indicative of the phase relationship between said clock signal and said reference signal;
• and
• means for injecting said preamble portion into said oscillator.

A method for providing a clock signal having a predetermined phase and frequency relationship with respect to a received signal, said received signal comprising a preamble portion and a data portion, said method comprising the steps of:

• (a) providing a phase lock loop including
• a voltage-controlled oscillator having an injection input, for providing said clock signal,
• a local frequency reference for generating a reference signal, and
• phase detector means for providing a control signal to said oscillator indicative of the phase relationship between said clock signal and said reference signal;
• and
• (b) injecting said preamble portion into said oscillator to provide said clock signal.