Programmable logic device

A programmable logic device comprising,

• a plurality of programmable logic arrays, each programmable logic array having a set of inputs and a set of outputs,
• a first set of conductive lines, each conductive line including a main line permanently connected to an output of one of said programmable logic arrays and a plurality of branching lines connected to said main line by series switches,
• a second set of conductive lines, each conductive line of said second set including a main line permanently connected to an input of one of said programmable logic arrays and a plurality of branching lines connected to said main line by series switches,
• wherein said branching lines of said first and second sets of conductive lines cross at areas forming programmable interconnection matrices, said matrices including programmable links at the intersections of each branching line of the first set with a branching line of the second set, each of said links being switchable so as to selectively connect any output of a programmable logic array to an input of a programmable logic array,
• a plurality of input pins selectively connected to at least one conductive line of said second set, and
• a plurality of output pins selectively connectable to at least one conductive line of said first set.

A programmable logic device comprising,

• first and second subunits, each of said subunits having a matrix of functional units, each functional unit having a set of inputs and a set of outputs and being individually programmable for carrying out a specified logic function, each subunit also having a first set of conductive lines, each line being permanently connected to an output of one of said functional units, a second set of conductive lines, each line of said second set being permanently connected to an input of one of said functional units, said first and second set of conductive lines crossing at programmable interconnection matrices, said matrices including programmable links at the intersections of said conductive lines, a plurality of input pins connected to at least one input line, said input line being programmably connectable to said second set of conductive lines at programmable interconnection matrices, and a plurality of output pins connected to at least one output line, said output line being programmably connectable to said first set of conductive lines at programmable interconnection matrices, and
• a switching matrix disposed between said first and second subunits, said switching matrix having central connect lines programmably connected to said at least one input line and said first set of conductive lines of each said subunit, said switching matrix also having two sets of lead lines connectable to said central connect lines, each set of lead lines being programmably connectable to said at least one output line and said second set of conductive lines of one said subunit.