Non-stacked ECL type and function
AssigneeTexas Instruments Incorporated
InventorKevin M. Ovens
Life of this patent
Estimating the term…
Abstract
A logic circuit which includes first and second differentially connected amplifying devices having first and second complementary output voltage nodes. Means for limiting the output voltage swing of the devices at the output nodes to a predetermined range reduces the required voltage supply source. A reference voltage is coupled to the second amplifying device while a plurality of input diodes are coupled in parallel to an input of the first amplifying device to form AND inputs thereto. A biasing element is coupled to the input of the first amplifying device.
Claims23
A logic circuit comprising:
- first and second differentially connected transistors having first and second complementary output nodes at respective first and second collectors;
- means for limiting the output voltage swing of at least one of said collectors to a predetermined range, said limiting means coupled between ground potential and said at least one collector;
- a reference voltage coupled to an input of said second transistor;
- a supply voltage coupled to respective first and second emitters of said transistors;
- a plurality of input diodes having anodes commonly coupled to an input of said first transistor forming AND inputs thereto;
- and
- biasing means coupled to the input of said first transistor.
A logic circuit comprising:
- first and second differentially connected transistors having commonly connected emitters coupled to a low voltage supply line;
- a first diode having a high forward bias voltage parallel connected with a series connected second diode and first resistor, said second diode having a low forward bias voltage, the first diode, second diode and first resistor coupled between a high voltage supply line and a collector of one of said first or second transistors for establishing a predetermined voltage drop from said high voltage line to said collector;
- a reference voltage having a voltage intermediate said high voltage and low voltage supply coupled to a base of said second transistor;
- a plurality of input diodes having a low forward bias voltage and having their anodes commonly coupled to a base of said first transistor, signals transmitted by said input diodes forming AND inputs to said base of said first transistor;
- and
- a biasing means coupled between the base of said first transistor and the high voltage supply line for biasing on said first transistor when the inputs to said input diodes are all high.
An emitter-coupled logic circuit combining AND and OR logic comprising
- at least a first and a second transistor connected in parallel, said first and second transistors differentially connected to a third transistor, said first, second and third transistors having commonly connected emitters;
- a resistor coupled between said emitters of said transistors and a low voltage supply source;
- means for supplying input signals to a base of each of said first and second transistors;
- means for biasing said first and second transistors coupled between said bases of said first and second transistors and a high voltage supply source;
- a reference voltage source connected to a base of said third transistor;
- first means for limiting the output voltage swing of commonly connected collectors of said first and second transistors coupled between said commonly connected collectors and said high voltage supply source;
- and
- second means for limiting the output voltage swing of a collector of said third transistor coupled between said collector of said third transistor and said high voltage supply source.
Dependencies are inferred from the claim text.