Differential amplifier having controllable power consumption

A differential amplifier having two parallel circuit branches lying between a first circuit node and a first supply voltage terminal, each of these parallel circuit branches containing a load element and a field effect transistor, having a further circuit branch lying between said first circuit node and a second supply voltage terminal, said further circuit branch having a constant current source whereby a quiescent current supplied by the latter is divided onto both parallel circuit branches, and having two, further field effect transistors serving as controllable current sources and connected parallel to the constant current source, these further field effect transistors supplying auxiliary currents amplifying the quiescent current, whereby gate terminals of the field effect transistors in the parallel circuit branches receive an input signal, and an output signal can be taken at the junctions between the load elements and the field effect transistors in the parallel circuit branches, comprising

• the field effect transistors in the parallel circuit branches and the further field effect transistors are of an n-channel type;
• a level-converting circuit having first and second inputs connected to gate terminals, respectively, of the field effect transistors in the parallel circuit branches, said level-converting circuit converting a d.c. component of an input signal present at the first and second inputs to a lower output level at first and second outputs, the first and second outputs of said level-converting circuit wired to gate terminals, respectively, of the further field effect transistors, the level converting circuit converting the d.c. component of the input signal being composed of a differential amplifier stage which contains two current branches lying between a further circuit node and the second supply voltage terminal, each of these current branches having a series circuit of two field effect transistors of different channel types;
• the further circuit node connected to the first supply voltage terminal via a current source transistor of a p-channel type;
• gate terminals of one of the field effect transistors of the current branches corresponding to the channel type of the current source transistor and forming the first and second inputs;
• the junctions between the latter field effect transistors and the other two field effect transistors of the current branches representing the first and second outputs.

A differential amplifier having two parallel circuit branches lying between a first circuit node and a first supply voltage terminal, each of these parallel circuit branches containing a load element and a field effect transistor, having a further circuit branch lying between said first circuit node and a second supply voltage terminal, said further circuit branch having a constant current source whereby a quiescent current supplied by the latter is divided onto both parallel circuit branches, and having two, further field effect transistors serving as controllable current sources and connected parallel to the constant current source, these further field effect transistors supplying auxiliary currents amplifying the quiescent current, whereby gate terminals of the field effect transistors in the parallel circuit branches receive an input signal, and an output signal can be taken at the junctions between the load elements and the field effect transistors in the parallel circuit branches, comprising the field effect transistors in the parallel circuit branches and the further field effect transistors are of a p-channel type;

• and a level-converting circuit having an input side connected to gate terminals of the field effect transistors in the parallel circuit branches, said level-converting circuit converting a d.c. component of an input signal to a higher output level, an output side of said level-converting circuit wired to gate terminals of the further field effect transistors.

A differential amplifier having two parallel circuit branches lying between a first circuit node and a first supply voltage terminal, each of these parallel circuit branches containing a load element and a field effect transistor, having a further circuit branch lying between said first circuit node and a second supply voltage terminal, said further circuit branch having a constant current source whereby a quiescent current supplied by the latter is divided onto both parallel circuit branches, and having two, further field effect transistors serving as controllable current sources and connected parallel to the constant current source, these further field effect transistors supplying auxiliary currents amplifying the quiescent current, whereby gate terminals of the field effect transistors in the parallel circuit branches receive an input signal, and an output signal can be taken at the junctions between the load elements and the field effect transistors in the parallel circuit branches, comprising

• the field effect transistors in the parallel circuit branches and the further field effect transistors are of a p-channel type;
• a level-converting circuit having first and second inputs connected to gate terminals, respectively, of the field effect transistors in the parallel circuit branches, and said level-converting circuit converting a d.c. component of an input signal present at the first and second inputs to a higher output level at first and second outputs, the first and second outputs of said level-converting circuit wired to gate terminals, respectively, of the further field effect transistors, the level converting circuit converting the d.c. component of the input signal being composed of a differential amplifier stage which contains two current branches lying between a further circuit node and the second supply voltage terminal, each of these current branches having a series circuit of two field effect transistors of different channel types;
• the further circuit node connected to the first supply voltage terminal via a current source transistor of an n-channel type;
• gate terminals of one of the field effect transistors of the current branches corresponding to the channel type of the current source transistor and forming the first and second inputs;
• the junctions between the latter field effect transistors and the other two field effect transistors of the current branches representing the first and second outputs.