Phase locked motor control system for multiple disk drive units

A phase and frequency locked motor control system for controlling phase and frequency operation of a disk drive spindle motor, said system comprising:

• means for driving the spindle motor, said driving means including a motor power stage for supplying power to the motor, and a commutation logic for controlling operation of said power stage;
• means for generating a motor signal representative of motor rotating frequency and phase;
• means for generating a reference signal representative of a reference rotating frequency and phase;
• means for comparing said motor signal with said reference signal, said comparing means including means for generating an error signal representative of error between said motor signal frequency and phase and said reference signal frequency and phase;
• said comparing means comprising an error detector for generating a first output error signal representative of said motor signal leading said reference signal, and a second output error signal representative of said motor signal trailing said reference signal, said error detector generating said first and second output error signals one at a time, said comparing means further including an analog sample circuit including means for sampling and integrating the generated one of said first and second output error signals in a repetitive manner, a signal storage circuit, and means for transferring the signal integrated by said integrating means to said storage circuit to produce an analog error signal representative of said error
• means responsive to said analog error signal for modulating said analog error signal to produce a pulse width modulated motor control signal having a duty cycle representative of said error, and for coupling said motor control signal to said commutation logic for regulation operation of said power stage to drive the motor in phase and frequency locked relation with said reference signal.

A phase and frequency locked motor control system for controlling phase and frequency operation of a disk drive spindle motor, said system comprising:

• means for driving the spindle motor, said driving means including a motor, and a commutation logic for controlling operation of said power stage;
• means for generating a motor signal representative of motor rotating frequency and phase;
• means for generating a reference signal representative of a reference rotating frequency and phase;
• an error detector for receiving said motor signal and said reference signal and responding thereto to generate an output error signal representative of error between said motor signal frequency and/or phase and said reference signal frequency and/or phase, said output error signal comprising a first output error signal representative of said motor signal leading said reference signal and a second output error signal representative of said motor signal trailing said reference signal, said error detector generating said first and second output error signals one at a time;
• a sample circuit including means for sampling and integrating said output error signal to produce an analog error signal representative of said frequency and/or phase error;
• and
• a modulator circuit driven by said analog error signal to produce a pulse width modulated motor control signal having a duty cycle representative of said error, and for coupling said motor control signal to said commutation logic for regulating operation of said power stage to drive the motor in phase and frequency locked relation with said reference signal.

A phase and frequency locked motor control system for controlling phase and frequency operation of a disk drive spindle motor, said system comprising:

• means for driving the spindle motor, said driving means including a motor power stage for supplying power to the motor, and a commutation logic for controlling operation of said power stage;
• means for generating a motor signal representative of motor rotating frequency and phase;
• means for generating a reference signal representative of a reference rotating frequency and phase;
• an error detector circuit having first and second output ports, said error detector circuit including means for comparing said motor signal and said reference signal and responding thereto to produce an output error signal defined by a substantially constant output error signal at said first output port when said motor signal frequency trails said reference signal frequency, a pulse width modulated output error signal at said first output port and having a duty cycle representative of phase error when said motor signal frequency substantially matches said reference signal frequency and said motor signal phase trails said reference signal phase, a substantially constant output error signal at said second output port when said motor signal frequency leads said reference signal frequency, and a pulse width modulated output error signal at said second output port when said motor signal frequency substantially matches said reference signal frequency and said motor signal phase leads said reference signal phase;
• an analog sample circuit including a first analog switch coupled to said first output port and a second analog switch coupled to said second output port, said first and second switches closing in response to said output error signal at the associated one of said output ports, integrator means for integrating and storing a charge in accordance with the time closure period of said analog switches, said charge defining an analog error signal;
• and
• means for modulating said analog error signal to produce a pulse width modulated motor control signal having a duty cycle representative of error between said motor and reference signals, and for coupling said motor control signal to said commutation logic for regulating operation of said power stage to drive the motor in phase and frequency locked relation with said reference signal.

A method of controlling phase and frequency operation of a disk drive spindle motor having a motor power stage circuit for supplying power to the motor and a commutation logic circuit for controlling operation of said power stage circuit, said method comprising:

• generating a motor signal representative of motor rotating frequency and phase;
• generating a reference signal representative of a reference rotating frequency and phase;
• comparing said motor signal and said reference signal and for generating in response thereto an output error signal representative of error between the motor signal and the reference signal;
• said comparing step including the steps of generating a first output error signal when said motor signal frequency trails said reference signal frequency, a second output error signal when said motor signal frequency leads said reference signal frequency, a third output error signal when said motor signal frequency substantially matches said reference signal frequency and said motor signal phase trails said reference signal phase, and a fourth output error signal when said motor signal frequency substantially matches said reference signal frequency and said motor signal phase leads said reference signal phase, said error signal generating step including generating the first through fourth output signals one at a time in accordance with the frequency and phase of the motor signal relative to the reference signal;
• converting the output error signal to a pulse width modulated motor control signal having a duty cycle representative of said error;
• and
• coupling the motor control signal to the commutation logic circuit for regulating operation of said power stage circuit to drive the motor in phase and frequency locked relation with the reference signal.

A method of controlling phase and frequency operation of a disk drive spindle motor having a motor power stage circuit for supplying power to the motor, and a commutation logic circuit for controlling operation of said power stage circuit, said method comprising:

• generating a motor signal representative of motor rotating frequency and phase;
• generating a reference signal representative of a reference rotating frequency and phase;
• comparing said motor signal and said reference signal and for generating in response thereto an output error signal representative of error between the motor signal and the reference signal;
• converting the output error signal to a pulse width modulated motor control signal having a duty cycle representative of said error;
• and
• coupling the motor control signal to the commutation logic circuit for regulating operation of said power stage circuit to drive the motor in phase and frequency locked relation with the reference signal;
• said comparing step comprising generating one at a time a first output error signal representative of the motor signal leading the reference signal, and a second output error signal representative of the motor signal trailing the reference signal, said comparing step further including sampling and integrating the generated one of said first and second output error signals in a repetitive manner, and transferring the resultant integrated signal to a signal storage circuit to produce an analog error signal representative of the error between the motor and reference signals.

A method of controlling phase and frequency operation of a disk drive spindle motor having a motor power stage circuit for supplying power to the motor, and a commutation logic circuit for controlling operation of said power stage circuit, said method comprising:

• generating a reference signal representative of motor rotating frequency and phase;
• generating a reference signal representative of a reference rotating frequency and phase;
• comparing the motor signal and the reference signal and responding thereto to generate an output error signal representative of error between the motor signal and the reference signal, said comparing step comprising the steps of generating one at a time a first output error signal representative of the motor signal leading the reference signal and a second output error signal representative of the motor signal trailing the reference signal;
• sampling and integrating the output error signal to produce an analog error signal representative of said error;
• pulse width modulating the analog error signal to produce a pulse width modulated motor control signal having a duty cycle representative of the error;
• and
• coupling the motor control signal to said commutation logic circuit for regulating operation of said power stage circuit to drive the motor in phase and frequency locked relation with the reference signal.