Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block

A semiconductor memory device including a programmable redundancy circuit, comprising:

• a plurality of memory cells and at least one spare memory cell,
• block selecting means for generating a block selecting signal and a block non-selecting signal,
• each of said memory cell array blocks being selected by said block selecting signal and not selected by said block non-selecting signal,
• a plurality of decoders each provided in each of said memory cell array blocks and responsive to address signals for selecting any of said memory cells,
• a plurality of spare sub-decoders each provided in each of said memory cell array blocks for selecting spare memory cell in place of a defective memory cell when said defective memory cell exists in said memory cells,
• a spare main decoder arranged outside said memory cell array blocks,
• said spare main decoder being responsive to an address signal corresponding to a defective memory cell in a selected memory cell array block and the block selecting signal for generating a spare decoder selection signal, and
• a spare decoder selecting line connected between said spare main decoder and said memory cell array block selected by said block selecting signal and said memory cell array block non-selected by said block non-selecting signal for transmitting said spare decoder selecting signal generated by said spare main decoder to said selected and non-selected memory cell array blocks,
• said spare sub-decoders being activated by said spare decoder selecting signal.