Wideband (DC-50 GHz) MMIC FET variable matched attenuator

A FET variable absorptive attenuator having an input and output and including a plurality of FETs connected between the input and the output and utilized as variable resistors controlled by voltages applied to their gate terminals, comprising:

• a first series FET, a distributed shunt FET, and a second series FET connected in a T configuration;
• the distributed shunt FET being split into a plurality of cells to provide low resistance when the cells of the distributed shunt FET are zero-biased at relatively high attenuation settings;
• a plurality of inductive reactances interconnected between adjacent cells of the distributed shunt FET;
• the combination of the resistances of the adjacent cells of the distributed shunt FET and the interconnected inductive reactances forming an LR circuit when the cells of the distributed shunt FET are zero-biased at relatively high attenuation settings and relatively high frequencies so that the voltage drop across the equivalent inductive reactance of the LR circuit is relatively greater than the voltage drop across the equivalent resistance of the LR circuit;
• a first voltage supply for providing a first control voltage to adjust the resistances of the first and second series FETs;
• and
• a second voltage supply for providing a second control voltage to adjust the resistance of the shunt FET;
• whereby the distributed shunt FET provides a low insertion loss at maximum attenuation, as well as decreases the parasitic capacitance of the shunt FET which can be more effectively compensated for by the inductive reactances thereby extending the dynamic range of attenuation at relatively high frequencies;
• and
• whereby the inductive reactances compensate for the parasitic capacitance of the series FETs at relatively high attenuation settings thereby yielding increased attenuation with increasing frequency and increasing the cutoff frequency of the attenuator at relatively low attenuation settings.

A FET variable absorptive attenuator having an input and output and including a plurality of FETs connected between the input and the output and utilized as variable resistors controlled by voltages applied to their gate terminals, comprising:

• a first series FET, a distributed shunt FET, and a second series FET connected in a T configuration;
• the distributed shunt FET being split into a plurality of cells;
• a plurality of inductive reactances interconnected between adjacent cells of the distributed shunt FET;
• a first voltage supply for providing a first control voltage to adjust the resistances of the first and second series FETs;
• a second voltage supply for providing a second control voltage to adjust the resistance of the shunt FET;
• the first series FET having its drain connected to the input, its gate connected to the first voltage supply, and its source connected to a first inductive reactance;
• the distributed shunt FET being split into n cells, each cell having its drain connected between respective inductive reactances n and n+1, its gate connected to the second voltage supply, and its source connected to common;
• and
• the second series FET having its source connected to the inductive reactance n+1, its gate connected to the first voltage supply, and its drain connected to the output;
• whereby the distributed shunt FET provides a low insertion loss at maximum attenuation, as well as decreases the parasitic capacitance of the shunt FET which can be more effectively compensated for by the inductive reactances thereby extending the dynamic range of attenuation at relatively high frequencies;
• and
• whereby the inductive reactances compensate for the parasitic capacitance of the series FETs at relatively high attenuation settings thereby yielding increased attenuation with increasing frequency and increasing the cutoff frequency of the attenuator at relatively low attenuation settings.

A FET variable absorptive attenuator having an input and output and including a plurality of FETs connected between the input and the output and utilized as variable resistors controlled by voltages applied to their gate terminals to provide a single-pole-single-throw switch, comprising:

• a first series FET, a shunt FET, and a second series FET connected in a T configuration;
• a pulse source connected to the first and second series FETs and the shunt FET for providing a first voltage level and a second voltage level, the first voltage level being applied to the first and second series FETs to gate the first and second series FETs ON and the second voltage level being applied to the shunt FET to gate the shunt FET OFF, thereby closing the switch, and, alternatively, the second voltage level being applied to the first and second series FETs to bias the first and second series FETs well below their pinch-off voltages to gate the first and second series FETs OFF and the first voltage level being applied to the shunt FET to gate the shunt FET ON, thereby opening the switch;
• a first resistor connected in parallel with the first series FET, the first resistor having a predetermined resistance depending on the output impedance of an external circuit connected to the input of the attenuator;
• and
• a second resistor connected in parallel with the second series FET, the second resistor having a predetermined resistance depending on the input impedance of an external circuit connected to the output of the attenuator;
• whereby the first and second resistors improve the isolation at relatively high frequencies thereby increasing the bandwidth of the switch.