High slew rate linear amplifier

An amplifier circuit for operation at reduced quiescent current levels and having complementary symmetrical signal channels from double-ended input stage to single-ended output stage, the circuit comprising:

• bias means for supplying bias signals of opposite polarity on separate conductors;
• an output stage having a first pair of complementary conductivity type transistors;
• a second pair of complementary conductivity type transistors in the output stage coupled to drive respective ones of said first pair of transistors;
• an input stage including at least one pair of transistors coupled to receive applied signal;
• source means connected to supply current of controllable level to the second pair of transistors in the output stage;
• means coupling the output of the input stage to drive said second pair of transistors in the output stage;
• and
• circuit means connected to the transistors in the input stage for supplying control signals to the source means to control the level of current supplied thereby to said second pair of transistors in response to signal level in the input stage.

An amplifier circuit for operation at reduced quiescent current levels and having complementary symmetrical signal channels from double-ended input stage to single-ended output stage, the circuit comprising:

• bias means for supplying bias signals of opposite polarity on separate conductors;
• an output stage having a first pair of complementary conductivity type transistors;
• a second pair of complementary conductivity type transistors in the output stage coupled to drive respective ones of said first pair of transistors;
• an input stage including at least one pair of transistors coupled to receive applied signal;
• said transistors in the input stage including in each channel a pair of transistors of the same conductivity type having emitter and base electrodes commonly connected and having collector electrodes;
• a resistor connecting one of said collector electrodes and a conductor of said bias means;
• and
• source means connected to supply current of controllable level to the second pair of transistors in the output stage;
• means coupling the output of the input stage to drive said second pair of transistors in the output stage;
• and
• circuit means connected to the transistors in the input stage for supplying control signals to the source means in response to the level of current in the input stage;
• said circuit means including an auxiliary transistor of said same conductivity type coupled to receive the signal across said resistor and connected between the conductor of the bias means and another of said collector electrodes for supplying a control signal on said another collector electrode to the source means.

Differential amplifier circuit for operation at reduced quiescent current levels, the circuit comprising:

• an output stage having a transistor coupled to receive bias current and an applied signal;
• an input stage including at least one pair of transistors coupled to form inverting and non-inverting inputs for receiving applied signals thereon;
• source means connected to supply bias current of controllable level to the transistor in the output stage;
• means coupling the pair of transistors in the input stage to supply signal to the transistor in the output stage;
• and
• circuit means connected to the input stage for supplying control signals to the source means for increasing the level of bias current supplied thereby to the transistor in the output stage in response to an increased signal level in the input stage.