High-speed analog multiplier--absolute value detector

A high-speed analog multiplier circuit comprising:

• a differential amplifier having a negative input, a positive input and an analog resultant output,
• a first pair of transistors (T1, T4) having outputs connected together and to the positive input of said amplifier,
• a second pair of transistors (T2, T3) having outputs connected together and to the negative input of said amplifier,
• a comparator having a multiplier input (X) and a real output (Q) and an inverted output Q,
• said real output (Q) being connected to a gate of one of said transistors (T1, T2) of one of each pair of said transistors (T1, T4 and T2, T3),
• said inverted output (Q) being connected to a gate of other ones of said transistors (T3, T4) of each pair of said transistors,
• a multiplicand input (Y) connected to an input of one of said transistors (T1, T3) of one of each pair of said transistors (T1, T4 and T2, T3),
• a reference voltage connected to an input of other ones of said transistors (T2, T4) of each pair of transistors, and
• said multiplier circuit performing the analog multiplication of multiplier (X) times the multiplicand (Y) to produce the analog result signum (X).multidot.Y.