Compensation circuit for nullifying differential offset voltage and regulating common mode voltage of differential signals

A method of controlling DC differential offset of a differential amplifier that provides first and second differential output signals having a differential offset voltage therebetween, said method comprising the steps of:

• isolating DC components from AC components of each of the first and second differential signals;
• summing the AC component of the first differential signal with the DC component from the second differential signal to provide a first sum signal;
• summing the AC component of the second differential signal with the DC component of the first differential signal to provide a second sum signal;
• providing the first and second sum signals to an operational amplifier to provide an output signal responsive to the voltage difference between said first and second sum signals;
• and
• providing the output signal from the operational amplifier as an input signal to a DC differential offset control input of the differential amplifier to control the DC differential offset of the differential amplifier to reduce the difference between the first and second sum signals, thereby reducing the difference between the DC components of the first and second differential output signals from said differential amplifier.

A compensation circuit that receives first and second differential input signals from a differential amplifier and that provides two differential output signals having a substantially constant common mode voltage of a predetermined magnitude responsive to a predetermined reference voltage, comprising:

• a first circuit that is responsive to a differential offset voltage between said first and second differential input signals from said differential amplifier and that provides a feedback signal to said differential amplifier to adjust DC differential offset of said differential amplifier so that said differential offset voltage is substantially equal to zero;
• a second circuit that receives a first input signal responsive to the common mode voltage of said first and second differential input signals from said differential amplifier and a second input signal that is responsive to said predetermined reference voltage, said second circuit providing an output signal responsive to the difference between said first input signal and said second input signal;
• and
• a voltage divider network that receives said output signal from said second circuit and that receives said differential input signals from said differential amplifier, said voltage divider network providing first and second differential output signals that have said substantially constant common mode voltage of said predetermined magnitude.

A method of generating a pair of differential output signals having a known common mode voltage substantially equal to a predetermined reference voltage, comprising the steps of:

• receiving a pair of differential input voltages having an unknown common mode voltage;
• isolating a DC voltage level responsive to said unknown common mode voltage;
• providing said isolated DC voltage level as one input to an operational amplifier;
• providing a second signal responsive to said predetermined reference voltage as a second input to said operational amplifier;
• generating an restoration voltage output signal responsive to the difference between said isolated DC voltage level and said second signal;
• providing said restoration voltage output signal as an input to a voltage divider circuit;
• providing said pair of differential input signals as inputs to said voltage divider circuit;
• and
• providing a pair of differential output signals from said voltage divider circuit having a common mode voltage substantially equal to said reference voltage.

A signal processing apparatus, comprising:

• a differential amplifier having first and second inputs and first and second outputs, said first output producing a first output signal and said second output producing a second output signal, each of said first and second output signals having a DC component and an AC component, said DC components having unknown magnitudes;
• a compensation circuit, connected to receive said first and second output signals, that generates a feedback signal that is provided to said differential amplifier to adjust relative magnitudes of said DC components of said first and second output signals to be substantially equal;
• a control circuit, connected to receive said first and second output signals, said control circuit comparing a signal responsive to the DC component of at least one of said first and second output signals with a reference signal and adjusting the magnitudes of said DC components to provide first and second compensated output signals, each having a DC component with a known fixed magnitude;
• and
• a zero-crossing detector that compares said first and second compensated output signals and provides a detector output signal responsive to the relative magnitudes of said first and second compensated output signals.