Method of and circuit for generating bit-order modified binary signals

A method of sequentially generating binary address signals comprising:

• (a) storing in a first register, a binary index signal comprising a sequence of a predetermined number of bits,
• (b) storing in a second register, a binary base address signal comprising a sequence of said predetermined number of bits,
• (c) carrying out a reverse arithmetic addition from the most significant bits of said index signal and said base address signal for producing an initial output address signal representative of the arithmetic sum of the index and base address signals during an initial cycle of signal generating operation,
• (d) storing said initial output address signal in said second register and adding the initial output address signal to said index signal for producing an output address signal differing in bit pattern from said initial output address signal during the cycle of signal generating operation immediately subsequent to said initial cycle and storing the last named output address signal in said second register, and
• (e) thereafter carrying out a reverse arithmetic addition of said index signal from said first register and the output address signal produced during each of the successive cycles of signal generating operation for producing another output address signals produced during the immediately preceding cycle of signal generating operation.

A bit-order modifiable signal generator circuit, comprising

• (a) an adder circuit comprising the combination of a binary multi-stage adder/subtractor and a forward-reverse selective carry propagation network, the multi-stage adder/subtractor having functions to carry out both a forward arithmetic addition from the least significant bits forward and a reverse arithmetic addition from the most significant bits backward selectively under the control of said forward/reverse selective carry propagation network,
• (b) an index register operable for having programmably yet fixedly stored therein a binary index signal comprising a sequence of a predetermined number of bits, and
• (c) a signal register operable for having programmably yet fixedly stored therein a binary base signal comprising a sequence of said predetermined number of bits,
• (d) said adder circuit being responsive to the index signal output from said index register and to a binary signal output from said signal register for producing an output signal representative of the arithmetic sum of the index signal and the signal output from the signal register during each cycle of signal generating operation, and
• (e) said signal register being responsive to said output signal from said adder circuit for tentatively storing the output signal from the adder circuit and feeding back the signal to said adder circuit for being arithmetically added to said index signal during each cycle of signal generating operation.

A bit-order modifiable address generator circuit having functions to perform a fast Fourier transform algorithm with a predetermined number of sample points set therein, comprising

• (a) an adder circuit comprising the combination of a binary multi-stage adder/subtractor and a forward-reverse selective carry propagation network, the multi-stage adder/subtractor having functions to carry out both a forward arithmetic addition from the least significant bits forward and a reverse arithmetic addition from the most significant bits backward selectively under the control of said forward/reverse selective carry propagation network,
• (b) an index register operable for having programmably yet fixedly stored therein a binary index address signal comprising a sequence of a predetermined number of bits, the predetermined number of bits being uniquely determined depending upon said predetermined number of sample points set in said fast Fourier transform algorithm, and
• (c) an address register operable for having programmably yet fixedly stored therein a binary base address signal comprising a sequence of said predetermined number of bits,
• (d) said adder circuit being responsive to the index address signal output from said index register and to a binary address signal output from said address register for producing an output address signal representative of the arithmetic sum of the index address signal and the address signal output from the address register during each cycle of address generating operation, and
• (e) said address register being responsive to said output address signal from said adder circuit for tentatively storing the output address signal from the adder circuit and feeding back the address signal to said adder circuit for being arithmetically added to said index address signal during each cycle of address generating operation.

A bit-order modifiable generator circuit comprising:

• an adder comprising a multistage adder circuit and a forward reverse selective carry propagation network, the multistage adder circuit including means for selectively performing a reverse arithmetic addition from the most significant bits selectively under the control of the forward-reverse select carry propagation network;
• a first register having stored therein a first signal having a predetermined number of bits and the first register being operatively connected to provide a first input to the adder;
• and
• a second register operatively connected to receive and store a sum signal from the adder, to provide a second input to the adder and to provide as an output the generated bit-order modified signal.