Synchronizing signal generating circuit

A synchronizing signal generating circuit comprising:

• a field discriminating circuit for deriving a field discriminating signal from a composite synchronizing signal relative to a plurality of composite video signals having different numbers of scanning lines and produced from different video output devices;
• an F/V converter;
• an equalizing pulse remover and a vertical synchronizing signal separator which are controlled by said F/V converter, said F/V converter, said equalizing pulse remover, and said vertical synchronizing signal separator being receptive of the composite synchronizing signal;
• and a field detector including at least one delay flip-flop means and having a data input terminal connected to an output terminal of said equalizing pulse remover, a trigger input terminal connected to an output terminal of said vertical synchronizing signal separator, and a time constant control terminal connected to an output terminal of said F/V converter;
• said field discriminating circuit being arranged such that at a time or during a time period upon elapse of a time period from a prescribed leading edge of a rectangular-wave output signal from said vertical synchronizing signal separator, said field detector determines the binary level of an output signal applied by said equalizing pulse remover to said data input terminal for deriving the field discriminating signal of either a high level or a low level.

A synchronizing signal generating circuit comprising:

• a field discriminating circuit for deriving a field discriminating signal from a composite synchronizing signal relative to a plurality of composite video signals having different numbers of scanning lines and produced from different video output devices;
• a frequency synthesizer for multiplying a horizontal synchronizing signal based on said composite synchronizing signal;
• an F/V converter;
• an equalizing pulse remover and a vertical synchronizing signal separator which are controlled by said F/V converter, said F/V converter, said equalizing pulse remover, and said vertical synchronizing signal separator being receptive of the composite synchronizing signal;
• and a field detector including at least one delay flip-flop means and having a data input terminal connected to an output terminal of said equalizing pulse remover, a trigger input terminal connected to an output terminal of said vertical synchronizing signal separator, and a time constant control terminal connected to an output terminal of said F/V converter;
• said field discriminating circuit being arranged such that at a time or during a time period upon elapse of a time period from a prescribed leading edge of a rectangular-wave output signal from said vertical synchronizing signal separator, said field detector determines the binary level of an output signal applied by said equalizing pulse remover to said data input terminal for deriving the field discriminating signal of either a high level or a low level, the arrangement being such that an output signal from said equalizing pulse remover is applied to a reference input terminal of said frequency synthesizer to enable the frequency synthesizer to produce from an output terminal thereof a signal that is obtained by multiplying the horizontal synchronizing signal.

A synchronizing signal generating circuit comprising:

• a field discriminating circuit for deriving a field discriminating signal from a composite synchronizing signal relative to a plurality of composite video signals having different numbers of scanning lines and produced from different video output devices;
• a frequency synthesizer including at least a prescaler for multiplying a horizontal synchronizing signal based on said composite synchronizing signal;
• an F/V converter;
• an equalizing pulse remover and a vertical synchronizing signal separator which are controlled by said F/V converter, said F/V converter, said equalizing pulse remover, and said vertical synchronizing signal separator being receptive of the composite synchronizing signal;
• and a field detector including at least one delay flip-flop means and having a data input terminal connected to an output terminal of said equalizing pulse remover, a trigger input terminal connected to an output terminal of said vertical synchronizing signal separator, and a time constant control terminal connected to an output terminal of said F/V converter;
• said field discriminating circuit being arranged such that at a time or during a time period upon elapse of a time period from a prescribed leading edge of a rectangular-wave output signal from said vertical synchronizing signal separator, said field detector determines the binary level of an output signal applied by said equalizing pulse remover to said data input terminal for deriving the field discriminating signal of either a high level or a low level, the arrangement being such that an output signal from said equalizing pulse remover is applied to a reference input terminal of said frequency synthesizer and an output signal from said F/V converter is applied as a control signal as said prescaler to enable the prescaler to produce from an output terminal of said frequency synthesizer a signal that is obtained by multiplying the horizontal synchronizing signal.