Integrated circuit device having stacked conductive layers connecting circuit elements therethrough

An integrated circuit device, comprising:

• a stacked layer unit comprising stacked layers each layer including:
• an insulation layer;
• and
• a conductive layer formed on a surface of said insulation layer;
• a chip mounted on said stacked layer unit;
• first and second conductive means, formed in said stacked layer unit and connected to said chip, both for providing a conductive path to said chip, said first conductive means being supplied with a first signal of a first frequency and comprising:
• a first via hole formed in said stacked layer unit;
• and
• a first conductive material having first and second ends, in said first vial hole, said first end being connected to one of said conductive layers, and said second end being connected to another of said conductive layers, and having a first inductive property;
• and
• said second conductive means being supplied with a second signal of a second frequency lower than said first frequency and comprising:
• a second via hole formed in said stacked layer unit;
• and
• a second conductive material having first and second ends, in said second via hole, said first end being connected to one of said conductive layers and said second end being connected to another of said conductive layers, and having a second conductive property different from the first conductive property, said first conductive means exhibiting different inductive properties than the inductive properties exhibited by said second conductive means;
• and
• package means for enclosing and hermetically sealing said stacked layer unit and said chip.

An integrated circuit device, comprising:

• a stacked layer unit comprising stacked layers, each layer including
• an insulation layer, and
• a conductive layer formed on a surface of said insulation layer;
• a chip mounted on said stacked layer unit;
• first conductive means, formed in said stacked layer unit and electrically coupled to said chip, for providing a conductive path to said chip, comprising
• a first via hole formed in said stacked layer unit;
• and
• a first conductive material having a first inductance being positioned in said first via hole and having a first end connected to one of said conductive layers, and a second end connected to another of said conductive layers;
• second conductive means formed in said stacked layer unit and electrically coupled to said chip and having a second inductance, for providing a conductive path to said chip, comprising:
• a second via hole formed in said stacked layer unit, and
• a second conductive material having a second inductive property different from the first inductive property, being positioned in said second via hole and having a first end connected to one of said conductive layers and said second end being connected to another of said conductive layers;
• and
• package means for enclosing and hermetically sealing said stacked layer unit and said chip, said first conductive means having an inductance lower than that of said second conductive means, said first conductive means being supplied with a high frequency signal, said second conductive means being supplied with a power signal having a lower frequency than that of said high frequency signal.