Semiconductor integrated circuit device having gate array and memory and input-output buffer

A semiconductor integrated circuit device having a normal mode and a test mode for testing a memory thereof, said semiconductor integrated circuit device comprising:

• input/output buffer parts having input/output terminals;
• at least one gate array;
• at least one memory;
• a first interconnection for coupling said input/output buffer parts, said gate array and said memory, said first interconnection being routed depending on a logic operation to be carried out by said semiconductor integrated circuit;
• and
• a second interconnection for coupling said input/output buffer parts, said gate array and said memory, said second interconnection being fixed regardless of the logic operation to be carried out by said semiconductor integrated circuit,
• said input/output bufer parts comprising a first input/output part having a first terminal which is used in common as an input terminal of said first interconnection for receiving a normal input signal in the normal mode and an input terminal of said second interconnection for receiving a test signal in the test mode, and a second input/output part having a second terminal which is used in common as an output terminal of said first interconnection and an output terminal of said second interconnection.