Semiconductor resin package structure

A semiconductor resin package structure comprising:

• a semiconductor chip;
• and
• a carrier substrate which is soldered on one surface thereof to electrodes of said semiconductor chip according to the flip-chip connection method wherein solder connections extend from the carrier substrate to the electrodes of said semiconductor chip to form a gap between the carrier substrate and the semiconductor chip, the gap between said semiconductor chip and said carrier substrate being filled with resin having a thermal expansion coefficient which is equal to that of the solder forming the solder connections, the electrodes of said semiconductor chip being electrically connected with terminals of the other surface of said carrier substrate through the solder connections and at least one through-hole conductor disposed on said carrier substrate, the thermal expansion coefficient of said carrier substrate being approximately equal to that of a multi-layer substrate, with said carrier substrate is connected by soldering with said terminals;
• solder for connecting said carrier substrate with said multi-layer substrate having a melting point that is lower than the melting point of the solder for connecting said semiconductor chip with said carrier substrate.

A semiconductor mounting structure comprising:

• at least one semiconductor package structure formed according to flip-chip connection method and adopted to be cooled at the rear surface of semiconductor chip, each package including
• a semiconductor chip, and
• a carrier substrate which is soldered on one surface thereof to electrodes of said semiconductor chip according to the flip-chip connection method, the gap between said semiconductor chip and said carrier substrate being filled with resin having a thermal expansion coefficient, which is equal to that of used solder, the electrodes of said semiconductor chip being electrically connected with terminals on the other surface of said carrier substrate through the solder portions and a through-hole conductor disposed on said carrier substrate;
• a multi-layer substrate who which said carrier substrate is connected by soldering with said terminals, with solder whose melting point is lower than the melting point of the solder for connecting said carrier substrate with said multi-layer substrate, the thermal expansion coefficient of said carrier substrate being approximately equal to that of said carrier substrate;
• and
• means for cooling the rear side of the semiconductor chips.

A semiconductor package structure formed according to flip-chip connection method and adapted to be cooled at the rear surface of semiconductor chip, each package including

• a semiconductor chip, and
• a carrier substrate which is soldered on one surface thereof to electrodes of said semiconductor chip according to the flip-chip connection method, the gap between said semiconductor chip and said carrier substrate being filled with resin having a thermal expansion coefficient, which is equal to that of used solder, the electrodes of said semiconductor chip being electrically connected with pin leads provided in said carrier substrate by solder;
• a multi-layer substrate to which said carrier substrate is connected by inserting said pin leads therein, the thermal expansion coefficient of said carrier substrate being approximately equal to that of said carrier substrate;
• and
• means for cooling the rear side of the semiconductor chips.

A semiconductor mounting structure comprising:

• at least one semiconductor package structure formed according to flip-chip connection method and adapted to be cooled at the rear surface of semiconductor chip, each package including:
• a semiconductor chip, and
• a carrier substrate which is soldered on one surface thereof to electrodes of said semiconductor chip according to the flip-chip connection method, the electrodes of said semiconductor chip being electrically connected with pin leads provided in said carrier substrate by solder;
• a multi-layer substrate to which said carrier substrate is connected by inserting pin leads therein, the thermal expansion coefficient, which is equal to that of a multi-layer substrate;
• and
• means for cooling the rear side of the semiconductor chip.