US 4,825,174 AGranted

Symmetric integrated amplifier with controlled DC offset voltage

AssigneeAmerican Telephone and Telegraph Company, AT&T Bell Laboratories

InventorGeorge P. Vella-Coleiro

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Abstract

A symmetric integrated FET amplifier is disclosed which exhibits a DC offset voltage that is insensitive to power supply variations, as well as variations in the threshold voltages of the FETs forming the amplifier. These variations are known to be most prevalent in InP-based FET amplifier arrangements. The symmetry is achieved by using a pair of impedance matching elements in the input stage of the amplifier to essentially match the impedance of the input FET and its load element, and a matching buffer FET and diode level shifting arrangement are used to match similar elements present in the output branch of the amplifier structure. The impedance matching elements, as well as the level shifting diodes, may all be formed with FET structures to minimize fabrication problems. In accordance with the symmetric arrangement of the present invention, the output DC offset voltage will be maintained at zero volts, regardless of the variations noted above. A multistage symmetric amplifier may then be formed simply by directly connecting a number of single stage symmetric amplifiers together in series.

Claims16

Dependent claims

A symmetric integrated FET amplifier comprising

an input FET including a gate, source and drain, responsive to an applied input voltage signal;
input load means coupled between the drain of said input FET and a first power supply source;
first impedance matching means connected to the source of said input FET, said first impedance matching means comprising an impedance value essentially the impedance of said input load means;
second impedance matching means connected between said first impedance matching means and a second power supply source, said second impedance matching means comprising an impedance value essentially the impedance of said input FET;
a first buffer FET including a gate, source and drain, the gate being coupled to the drain of said input FET, the drain being coupled to said first power supply source;
first voltage level shifting means coupled between the source of said first buffer FET and the amplifier output, said first voltage level shifting means for supplying a predetermined DC voltage drop to the signal appearing at the gate of said first buffer FET;
a second buffer FET including a gate, source and drain, the gate being coupled to the connection between said first and second impedance matching means and the source being coupled to the first voltage level shifting means at the amplifier output, said second buffer FET being essentially identical in size to said first buffer FET;
and
second voltage level shifting means coupled between the drain of said second buffer FET and said second power supply source, said second voltage level shifting means for supplying said predetermined DC voltage to the signal appearing at the gate of said second buffer FET.

6 more elements

A multistage integrated FET amplifier comprising a plurality of N separate stages directly connected in series, each separate amplifier stage comprising

an input FET including a gate, source and drain, responsive to an applied input voltage signal;
input load means coupled between the drain of said input FET and a first power supply source;
first impedance matching means connected to the source of said input FET, said first impedance matching means comprising an impedance value essentially the impedance of said input load means;
second impedance matching means connected between said first impedance matching means and a second power supply source, said second impedance matching means comprising an impedance value essentially the impedance of said input FET;
a first buffer FET including a gate, source and drain, the gate being coupled to the drain of said input FET, the drain being coupled to said first power supply source;
first voltage level shifting means coupled between the source of said first buffer FET and the amplifier output, said first voltage level shifting means for supplying a predetermined DC voltage drop to the signal appearing at the gate of said first buffer FET;
a second buffer FET including a gate, source and drain, the gate being coupled to the connection between said first and second impedance matching means and the source being coupled to the first voltage level shifting means at the amplifier output, said second buffer FET being essentially identical in size to said first buffer FET;
and
second voltage level shifting means coupled between the drain of said second buffer FET and said second power supply source, said second voltage level shifting means for supplying said predetermined DC voltage to the signal appearing at the gate of said second buffer FET.

6 more elements

Dependencies are inferred from the claim text.