MOS selfchecking microprogrammed control unit with on-line error detection

An MOS selfchecking microprogram control unit with on-line error detection, comprising:

• a microinstruction memory (MIM1) generating at an output thereof in the event of a failure only unidirectional errors, said microinstruction memory containing microinstructions each containing, in addition to a microinstruction datum field, two further fields consisting respectively of a current address code (CS) of a position in the microinstruction memory (MIM1) at which the microinstruction is physically contained and a future address code (FS) of a position in the microinstruction memory (MIM1) at which the next microinstruction is physically contained, said microinstructions including conditional-jump microinstructions being allocated in said microinstruction memory (MIM1) with codes related to one another by gating logic relationships and determining jumps to respective addresses according to a value of a variable;
• a temporary storage microinstruction register (MIR1) connected to said output of said microinstruction memory (MIM1);
• a first register counter (RCT1) connected to said temporary storage microinstruction register (MIR1);
• a second register counter (RCT2) connected to said first register counter (RCT1);
• a first condition selector (SEL1) connected to said temporary storage microinstruction register (MIR1) and to said first register counter (RCT1);
• a second condition selector (SEL2) connected to said second register counter (RCT2) and to said first condition selector (SEL1);
• a programmed-logic-array control signal generator (DSC1) having an input connected to an output of said temporary storage microinstruction register (MIR1) and generating in the event of failure only unidirectional errors at outputs of the programmed-logic-array control signal generator, said programmed-logic-array control signal generator (DSC1) being connected to said temporary storage microinstruction register (MIR1) and to said second condition selector (SEL2);
• a microprogram counter comprising an incrementer (INC1) connected to said microinstruction memory (MIM1) and a microprogram counter register (MPR1) connected to said incrementer (INC1), said incrementer (INC1) and said microinstruction memory (MIM1) receiving external inputs through a bus (IND);
• a temporary address memory (STK1) of stack-point addresses of a main instruction sequence haivng an input connected to an output of said microprogram counter register (MPR1), said temporary address memory (STK1) including a first selfchecking equality checker (VA1) for checking results of operations on control signals for registers of the temporary address memory (STK1), said temporary address memory (STK1) having an output connected to said bus (IND);
• a code-regeneration selfchecking microinstruction checker (CCK1) connected to said second register counter (RCT2), to said second condition selector (SEL2), to said programmed-logic-array control signal generator (DSC1) and to said temporary storage microinstruction register (MIR1);
• means connected to said temporary storage microinstruction register (MIR1) and responsive to said current address code (CS) and said future address code (FS) and controlled by said first condition selector (SEL1) for comparing a current address code (CS) of a particular microinstruction from said temporary storage microinstruction register (MIR1) with a future address code (FS) from a prior microinstruction from the temporary storage microinstruction register (MIR1) delayed by a microinstruction time and present in the prior microinstruction modified by said logic relationships as determined by said first condition selector (SEC1) and emitting a first error indication (ER2) upon a discrepancy in the comparison to effect a self-check of jump microinstruction;
• said incrementer (INC1) being connected to and receiving inputs from said bus (IND) being constructed to generate upon possible circuit failures only unidirectional errors on address outputs to said microprogram counter register (MPR1) in the event of failures at address inputs thereto and to output a second error indication (ER3) upon development of arithmetical errors involving internal carry signals;
• and
• means for applying control signals generated by said programmed-logic-array control signal generator (DSC1) to said temporary address memory (STK1) of stack-point addresses whereby said temporary address memory (STK1) is controlled by the control signals received from said programmed-logic-array control signal generator (DSC1) and which are carried to said first selfchecking equality checker (VA1) emitting a third error indication (ER4) upon a failure of the control signals from said programmed-logic-array control signal generator (DSC1),
• said code-regeneration selfchecking microinstruction checker (CCK1) generating a microinstruction code from words passed from said temporary storage microinstruction register (MIR1) through said register counters (RCT1) and (RCT2), and from control signals from said temporary storage microinstruction register (MIR1), said second condition selector (SEL2) and said programmed-logic-array control signal generator (DSC1) and comparing the thus-generated microinstruction code with a microinstruction code contained in the microinstruction emitted by said temporary storage microinstruction register (MIR1) to emit a fourth error signal (ER1) upon a comparison discrepancy.