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AssigneeIntel Corporation
InventorsMichael T. Imel, Konrad Lai, Glenford J. Myers, Randy Steck, James Valerio
Estimating the term…
Apparatus for performing mixed precision calculations in the floating point unit of a microprocessor from a single instruction opcode. 80-bit floating-point registers (44) may be specified as the source or destination address of a floating-point instruction. When the address range of the destination indicates (26) that a floating point register is addressed, the result of that operation is not rounded to the precision specified by the instruction, but is rounded (58) to extended 80-bit precision and loaded into the floating point register (FP-44). When the address range of the source indicates (26) that an FP register is addressed, the data is loaded from the FP register in extended precision, regardless of the precision specified by the instruction. In this way, real and long-real operations can be made to use extended precision numbers without explicitly specifying that in the opcode.
In a data processor including an instruction decoder (12) and a floating point unit (22) connected together by a microinstruction bus (29) which carries a current microinstruction generated by said decoder in the course of the decoding of a macroinstruction by said decoder, said macroinstruction including a source address field, a destination address field, and an opcode field, said opcode field including first means (LL0, LL1) specifying the precision of arithmetic operations specified by said macroinstruction, the improvement characterized by:
Dependencies are inferred from the claim text.