Reconfigurable dual processor system

A processing system comprising:

• a first and a second processor;
• a first main memory included in the first processor and a second main memory included in the second processor, the first and second main memories duplicating each other's contents;
• means interconnecting the first and the second main memories, when active for automatically updating each main memory with content changes being made in the other main memory to cause the first and second main memories to continue having the same contents;
• and
• means for automatically changing system operation from a first to a second mode of operation transparently to execution of application tasks in response to certain conditions, wherein in the second mode both processors are active and each is executing substantially independently of the other tasks selected from a different one of a first and a second group of tasks, and wherein in the first mode one of the processors is inactive and the other of the processors is active and executing tasks selected from both the first and the second group of tasks, the operation-changing means including means for causing the active other processor during the first mode of operation to change contents of the memory of the active other processor, thereby to effect like changes of contents of the memory of the one processor by way of the memory updating means copying the changed contents of the memory of the active other processor into the memory of the one processor, in order to prepare the one processor for becoming activated and to assign one of the groups of tasks to the one processor for execution during the second mode of operation, and further for causing the active other processor to activate the one processor in order to begin the second mode of operation.

A processing system comprising;

• as first and a second processor;
• a first main memory included in the first processor and a second main memory included in the second processor, the first and second main memories duplicating each other's contents;
• and
• means interconnecting the first and the second main memories, when active for automatically updating each main memory with content changes being made in the other main memory to cause the first and second main memories to continue having the same contents;
• and
• means cooperative with the memory updating means for automatically changing processor operation from any one to another of a first, a second, and a third mode of operation in response to certain conditions, the changes from one to another of the first and the second modes being transparent to execution of application tasks, wherein in the first mode both processors are active and each is executing substantially independently of the other programs selected from a different one of a first and a second group of tasks, wherein in the second mode one of the processors is active and executing tasks of both groups and the other of the processors is standing by ready to assume execution of tasks and wherein in the third mode one of the processors is active and executing tasks of both groups and the other of the processors is unavailable to assume execution of tasks.

In a processing system that includes a first and a second processor, a first main memory included in the first processor and a second main memory included in the second processor, the first and second main memories having the same contents including programs that include fault recovery programs and a first dispatch queue for holding identities of programs designated for execution, and apparatus interconnecting the first and second memories for automatically updating each main memory with content changes being made in the other main memory, a method of automatically changing system operation transparently to execution of application programs from a first state wherein the second processor is inactive and the first processor is active and executing programs selected from those indentified by the first dispatch queue to a second state wherein there are in each main memory the first and a second dispatch queue each for holding identities of programs designated for execution by a different one of the first and second processor, and wherein both processors are active an executing substantially independently of each other programs identified by their respective dispatch queues, the method comprising the step of:

• creating the second dispatch queue for identifying programs designated for execution by the second processor during the second mode of operation, in the main memory of the first processor thereby to effect like creation in the main memory of the second dispatch queue from the main memory of the first processor to the main memory of the second processor;
• creating shadow fault recovery programs comprising selected portions of the fault recovery programs for performing on the second processor fault recovery activities performable on a per-processor basis;
• setting the second processor to a known state to initialize the second processor;
• placing the identity of the shadow fault recovery programs in the second dispatch queue in the main memory of the first processor thereby to effect like placing in the main memory of the second processor by operation of the memory updating means;
• executing the shadow fault recovery programs on the second processor to ensure that the second processor may be entrusted with execution of application tasks in the second mode of operation;
• transferring the identity of programs, designated for execution by the second processor during the second mode of operation from the first to the second dispatch queue in the main memory of the first processor thereby to effect like transfer in the main memory of the second processor by operation of the memory updating means;
• starting the second processor to execute programs identified by the second dispatch queue to commence the second mode of operation;
• and
• continuing execution by the first processor of programs identified by the first dispatch queue.

In a processing system that includes a first and a second processor, an indicator arrangement for designating selectively either one of the processors as a primary processor and designating the other processor as a secondary processor, a first main memory included in the first processor and a second main memory included in the second processor, the first and second main memories having the same contents including programs that include the first and second main memories having the same contents including programs that include a first an a second program, fault recovery programs, and shadow fault recover programs comprising selected portions of the fault recover programs, and a first and a second dispatch queue for holding the identities of programs designated for execution by the primary and secondary processor, respectively, and apparatus interconnecting the first and second main memories for automatically updating each main memory with content changes being made in the other main memory, a method of automatically changing system operation transparently to execution of application programs from a first state wherein both processors are active and executing substantially independently of each other programs identified by their respective dispatch queues to a second state wherein the second processor is standing by ready to assume execution of programs and the first processor is active and executing programs selected from programs identified by the first dispatch queue, the method comprising the steps of:

• placing the identity of the first program in the dispatch queue of the second processor to initiate a change of system operation from the first to the second mode;
• commencing to execute the first program only when no interrupted programs are identified by the dispatch queue of the second processor to ensure that any processor state existent in the second processor during the first mode of operation and relating to an application task not completed by the second processor is stored by the second processor in the second processor's main memory and by operation of the memory updating means is copied from the second processor's main memory to the first processor's main memory to be available to the first processor for execution of the related application task during the second mode of operation;
• causing the second program to be executed on the second processor, in response to execution of the first program, the second program being executed without interruption to ensure that a processor state relating to an application task is not formed by the second processor during system transition between the first and second modes of operation;
• interrupting the first processor in response to execution of the second program to cause the first processor to complete the system transition from the first to the second mode of operation;
• stopping the second processor;
• moving identity of programs from the second dispatch queue to the first dispatch queue to designate for execution by the primary processor during the second mode of operation programs designated for execution by the secondary processor during the first mode of operation, in response to the interruption;
• removing the identity of shadow fault recovery programs from the first dispatch queue to avoid during subsequent program execution duplication of activities of the fault recovery programs;
• checking the indicator arrangement to determine whether the first processor is designated the primary processor;
• changing the indicator arrangement to switch the processors designations if the first processor is not designated the primary processor, to cause the first processor to select for execution programs from the first dispatch queue during the second mode of operation;
• and
• continuing to execute on the first processor programs identified by the first dispatch queue, in the second mode of operation.

In a processing system that includes a first and a second processor, an indicator arrangement for designating selectively either one of the processors as a primary processor and designating the other processor as a secondary processor, a first main memory included in the first processor and a second main memory included in the second processor, the first and second main memories having the same contents including programs that include fault recovery programs and shadow fault recovery programs comprising selected portions of the fault recovery programs, and a first and a second dispatch queue for holding the identities of programs designated for execution by the primary and secondary processor, respectively, and apparatus interconnecting the first and second main memories when active for automatically updating each main memory with content changes being made in the other main memory, a method of automatically changing system operation from a first state wherein both processors are active and executing substantially independently of each other programs identified by their respective dispatch queues to a second state wherein the second processor is out of service and the first processor is active and executing programs selected from programs identified by the first dispatch queue, the method comprising the steps of:

• stopping the second processor to terminate the first mode of operation;
• deactivating the main memory updating apparatus to cease updating of the main memory of the second processor with changes to the contents of the main memory of the first processor;
• moving the identities of programs from the second to the first dispatch queue to designate for execution by the primary processor during the second mode of operation programs designated for execution by the secondary processor during the first mode of operation;
• initializing the processes identified by the first dispatch queue to effect recovery of the processes from any events that lead to termination of the first mode of operation;
• removing identities of the shadow fault recovery programs from the first dispatch queue to avoid during subsequent program execution duplication of activities of the fault recovery programs;
• checking the indicator arrangement to determine whether the first processor is designated the primary processor;
• changing the indicator arrangement to switch the processors' designations if the first processor is not designated the primary processor to cause the first processor to select for execution programs from the first dispatch queue during the second mode of operation;
• and
• continuing to execute on the first processor programs identified by the first dispatch queue, in the second mode of operation.