MOS floating gate memory cell containing tunneling diffusion region in contact with drain and extending under edges of field oxide

A process for fabricating a nonvolatile MOS memory device including the steps of:

• first defining and doping a tunneling diffusion region in a semiconductor substrate,
• forming four opposed field oxide regions to define a four-sided active field effect transistor region in an area on said substrate which includes said tunneling diffusion region such that said tunneling diffusion region lies appreciably under the edges of two opposing ones of said field oxide regions,
• forming a first layer of dielectric material on top of said active field effect transistor regions, having a relatively thin portion therein disposed entirely over said tunneling diffusion region,
• forming a first gate electrode on top of said first layer of dielectric material, extending entirely over said thin portion,
• forming a second layer of dielectric material over and around said first gate electrode to electrically insulate said first gate electrode,
• forming a second gate electrode on top of said second layer of dielectric material, disposed entirely over said first gate electrode,
• forming source and drain regions in said active field effect transistor region at locations such that said tunneling diffusion region is in physical contact with said drain region and said tunneling diffusion region lies along the length of a channel formed by said source and drain regions.