Node architecture for communication networks
AssigneeRacal Data Communications Inc.
InventorsNandakishore A. Albal, Praduemn K. Goyal
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Abstract
An architecture for a switching node of a communication network includes a dedicated hardware Layer 1 processing portion and a Layer 2 and 3 processing portion based on multiple programmed general purpose processors. An array of such processors are used with an arbitration scheme for selecting which of the processors is to be used for any given Layer 2 or Layer 3 process. The architecture allows the node's capacity to be expanded by simply adding more processors to handle increased traffic.
Claims28
A node for a communication system for processing a D-Channel ISDN message, comprising in combination:
- interface means for receiving an ISDN signal from a transmission line;
- demultiplexing means for demultiplexing said ISDN signal into a D-Channel message and for performing Physical Layer processes on said D-Channel message;
- a processor bank including a plurality of processors which are interconnected by a bus for receiving said D-Channel message after said D-Channel message is processed by said demultiplexing means and for performing a Data Link Layer process on said D-Channel message;
- and
- arbitration means for determining which of said plurality of processors is to perform said Data Link Layer process on said D-Channel message.
A method for processing a D Channel ISDN message, comprising the steps of:
- receiving an ISDN signal from a transmission line;
- demultiplexing said ISDN signal to produce a D Channel message;
- performing a Physical Layer process on said D Channel message;
- selecting one of a plurality of available processors interconnected by a bus to perform a Data Link Layer process on said D Channel message.
Dependencies are inferred from the claim text.