Thin film transistor array for liquid crystal display panel

A thin film transistor array comprising an insulator substrate, a plurality of gate electrodes disposed on the insulator substrate in a matrix form composed of a plurality of columns and a plurality of rows, gate wiring layers connecting the gate electrodes in same rows in common, a first insulator film covering said gate electrodes, a plurality of semiconductor layers disposed on said first insulator film, each of said semiconductor layers locating above each of the gate electrodes and its periphery, a plurality of pairs of source and drain electrodes formed on said semiconductor layers, each pair of said source and drain electrodes contacting each one of said semiconductor layers to form a gap at a location above each of said gate electrodes, first column wiring layers connecting source or drain electrodes in same column in common, a second insulator film covering said source and drain electrodes and their gaps and said first column wiring layers and having apertures elongating in the column direction and exposing source or drain electrodes in every columns and said first column wiring layers, and second column wiring layers running in column direction on the second insulator film and in the elongating aperture and contacting with the exposed source or drain electrodes in every columns and with the exposed portion of said first column wiring layers through the elongating apertures.

A liquid crystal display panel having a thin film transistor array board, a common electrode board and liquid crystal interposed therebetween said thin film transistor array board comprising:

• a substrate of a transparent insulator;
• a plurality of gate electrodes formed in a matrix of columns and rows, said gate electrodes aligned in the same row being connected in common;
• a first insulator film formed on said substrate to cover said gate electrodes;
• a plurality of semiconductor islands formed on said first insulator locating on said gate electrodes and their peripheries, each of said semiconductor islands having a channel region locating above said gate electrode and source and drain regions locating on both sides of said channel region;
• a plurality of pixel electrodes respectively formed on said first insulator film adjacent to said source region of said semiconductor island;
• a plurality of source wirings respectively connecting said source region and said pixel electrode;
• a plurality of drain wirings respectively connecting said drain regions of said semiconductor islands located on said gate electrodes aligned in the same column;
• a second insulator film covering said source and drain wirings, said channel regions of said semiconductor islands and said pixel electrodes, said second insulator film having grooves exposing said drain wirings;
• a plurality of auxiliary wiring layers formed on said second insulator film, each of said auxiliary wiring layers filling respective one of said grooves to connect with said drain wiring exposed in said one of said grooves and;
• a plurality of light-shield layers, formed on said second insulator film located on said channel regions of said semiconductor islands, said light-shield layers being separated from said auxiliary wiring layers.