Operating system debugger

A multiprogrammable digital data processor comprising:

• A. memory means having addressable locations for storing process code signals associated with each of one or more processes, wherein the process code signals associated with each process include signals representative of at least one of instructions, data, and state values of that process,
• B. breakpoint means coupled with the memory means for replacing therein a signal representative of a selected instruction with a selected interrupt signal,
• C. scheduler means for scheduling one of said processes for execution during a designated time interval,
• D. first central processing unit means coupled to the memory means and to the scheduler means for normally executing the scheduled one of said processes during the designated time interval,
• E. said memory means further includes means for storing debugger process signals for placing said first central processing unit in a debugging operating mode for selectively
• i. suspending processing of the scheduled process by the first central processing unit means,
• ii. permitting selective access to locations of said memory means for at least one of modifying and outputting values of signals stored in those accessed locations,
• F. said debugger means further including simulation means for generating simulation code signals representative instructions for simulating the selected replaced instruction, and
• G. said debugger means further restart means for reactivating the suspended process for execution of at least said simulation code.

A method of operating a multiprogrammable digital data processor, said method comprising the steps of

• A. storing in a first storage element process code signals associated with each of one or more processes, wherein the process code signals associated with each process include signals representative of at least one of instructions, data, and state values of that process,
• B replacing in said first storage element a signal representative of a selected instruction with a selected interrupt signal,
• C. scheduling one of said processes for execution during a designated time interval,
• D. executing the scheduled one of said processes during the designated time interval,
• E. suspending processing of the scheduled process, and
• F. permitting selective access to locations of said first storage element for at least one of modifying and outputting values of signals stored in those accessed locations,
• G. generating simulation code signals representative instructions for simulating the selected replaced instruction, and
• H. reactivating the suspended process for execution of at least said simulation code.