Dielectrically stabilized GaAs FET oscillator with two power output terminals
AssigneeCom Dev Ltd.
InventorAntun Stajcer
Life of this patent
Estimating the term…
Abstract
A dielectrically stabilized planar GaAs FET oscillator has a single gate transistor with a gate terminal and a drain terminal. A cylindrically shaped dielectric resonator is mounted on a ceramic support. The dielectric resonator resonates in a TE.sub.01 mode and is located on the gate line of the transistor a predeterminated distance from the gate terminal. The transistor is biased so that the dielectric resonator alone can stabilize the power produced by the transistor. Stabilized output power is obtained from both the drain terminal and the gate terminal. With previous oscillators having a single gate transistor, output power could only be obtained from one terminal.
Claims11
A dielectrically stabilized planar GaAs FET oscillator comprising a housing containing a metal pattern on a dielectric substrate with backside metalization soldered to a carrier, said housing having a single gate transistor mounted therein, said transistor having a gate terminal and a drain terminal, with dielectric material located on a gate line of said transistor, said metal pattern being formed and said transistor being biased so that only the dielectric material is required to stabilize power at the frequency of interest and both terminals of said transistor can be made to supply microwave power simultaneously, while said dielectric material resonates in a TE.sub.01 mode, a power supply to the oscillator being a single negative supply voltage, the output power at the drain terminal being greater than that output power at the gate terminal.
Dependencies are inferred from the claim text.