Mobile incident logger
AssigneeStep Engineering
InventorsDarrell L. Wilburn, Darryl R. Plauck
Life of this patent
Estimating the term…
Abstract
Disclosed is a mobile incident logger for monitoring an on-board, automotive, computer and signal levels developed by analog and digital sensors, the logger employing a coverage monitor, which records which memory locations are accessed by the computer; a cycle tag counting unit, which counts bus cycles of the computer; a discriminator, which detects the occurrence of incidents the logger is to record; a trace memory unit, which stores bus states of the computer; a trace memory unit, which stores memory variables of the computer; a discriminator, which detects the occurrence of some of the incidents the logger is to record; and a trace memory unit, which stores the sensor signals.
Claims13
An apparatus for recording the states of data signals at times defined by a clocking signal, when the data signals meet at least one of a number of predetermined criteria, the apparatus comprising in combination:
- cycle tag counting means in response to the clocking signal develops signals representing a count of the cycles of said clocking signal;
- discriminator means having a predetermined number of outputs, said discriminator means in response to the data signals develops at each of said discriminator means outputs a signal the state of which indicates whether said data signals meet at least one of the criteria;
- and
- trace memory means including a predetermined number of portions each having
- counting means connected to said discriminator means, each of said trace memory means counting means in response store a corresponding one of said criteria indicating signals develops signals representing at least a count of the cycles of said corresponding one of said criteria indicating signals and
- random access memory means connected to said cycle tag counting means and having address inputs connected to the corresponding one of said trace memory means counting means, said trace memory means random access memory means in response to said data signals, said cycle tag counting means count signals, and ht respective trace memory means counting means count signals stores signal states representing both said data signals and said cycle tag counting means count signals when said data signals meet at least one of said criteria.
An apparatus for recording the states of data signals at times defined by a clocking signal, when the data signals meet predetermined criteria, the apparatus comprising in combination:
- cycle tag counting means in response to the clocking signal develops signals representing a predetermined bit length count other e cycles of said clocking signal and a signal indicating when said count rolls over;
- discriminator means having an output, said discriminator means in response to the data signals develops at said discriminator means output a signal the state of which indicates whether said data signals meet the criteria;
- and
- trace memory means including counting means connected to said discriminator means and to said cycle tag counting means, said trace memory means counting means in response to said criteria indicating signal and to said roll over indicating signal develops signals representing the sum of a count of the cycles of said criteria indicating signal and a count of the cycle of said roll over signal, an d random access memory means connected to said cycle tag counting means and having address inputs connected to said trace memory means counting means, said trace memory means random access memory means in response to said data signals, aid cycle tag counting means count signals, and said trace memory means counting means count signals stores signal state representing both said data signals and said cycle t ag counting means count signals when said data signals meet said criteria and stores signal state representing both said data signals and said cycle tag counting means count signals when said count rolls over.
A mobile incident logger for recording the state of signals which represent the bus state of a microprocessor of an on-board computer at times defined by a clocking signal developed by the microprocessor, the level of signals developed by a number of analog sensors, and th state of signals developed by a number of digital sensors, when the signals meet predetermined criteria, the logger comprising in combination:
- a clock generator in response to the microprocessor clocking signal develops a buffered clocking signal;
- first register means connected to said clock generator, said first register means in response to said buffer clocking signal and the microprocessor bus state signals latches the state of said microprocessor bus state signals at each of the times defined yb said buffered clocking signal and develops signals having said latched states;
- cycle tag counting means connected to said clock generator, said cycle t ag counting means in response to said buffer clocking signal develops signals representing a predetermined bit length count of the cycles of said buffered clocking signal and develops a signal indicating when said count rolls over;
- first discriminator means connected to said first register means and having at least one output, said first discriminator means in response to said latched state signals develops at said first discriminator means output a first signal the state of which indicates whether said latched state signals meet the criteria;
- and
- first trace memory means including counting means connected to said first discriminator means to and to said cycle tag counting means, said first trace memory means counting means in response to said first criteria indicating signal and to said roll over indicating signal develops signals representing the sum of a count of the cycle of said first criteria indicating signal and a count of the cycles of said roll over signal, and random access memory means having data inputs connected to said first register means and to said cycle tag counting means and having address inputs connected to said first trace memory means counting means, said first trace memory means random access memory means in response to said latched state signals. said cycle tag counting means count signals, and said first trace memory means counting means count signals stores signal state representing both said latched state signals and said cycle tag counting means count signals when said latched state signals meet said criteria and stores signal state representing both said latched state signals and said cycle tag counting means count signals when said count rolls over.
Dependencies are inferred from the claim text.