Synchronizer for a fault tolerant multiple node processing system

A Byzantine voter comprising:

• a voter memory having transverse and lateral rows and columns for storing a three-dimensional cube of data, said transverse and lateral rows and columns each having an equal number of bit positions;
• a data register connected to said vector memory having a plurality of bit positions, said plurality of bit positions at least equal to said number of bit positions in said transverse and lateral rows and columns of said voter memory;
• an address generator connected to said voter memory for generating addresses enabling said voter memory to unload said data stored in said rows and columns into said data register, one row or one column at a time in a selected sequence;
• a plurality of AND gates each having one input connected to a respective one of said bit positions in said data register, said AND gates each having a second input and an output;
• decoder means connected to said address generator and said AND gates responsive to said addresses generated by said address generator for generating individual signals applied to said second input of each of said plurality of AND gates, said decoder means generating an inhibit signal which deactivates one of said plurality of AND gates in a sequential manner each time new data is loaded into said data register;
• a plurality of multiplexers, one associated with each AND gate, each of said plurality of multiplexers having a first input connected to said output of its associated AND gate, each multiplexer further having a second input and an output;
• a message counter connected to said plurality of multiplexers for generating a reference number which is applied to said second input of each of said plurality of multiplexers, said reference number corresponding to a 2's complement of one half of the number of data values to be processed;
• a plurality of adders for generating sum data and voted data, each having a first input connected to said output of a respective one of said multiplexers, each of said adders having a second input, a sum output outputting said sum data and an overflow output outputting said voted data;
• a plurality of accumulators for storing said sum data, each accumulator having an input connected to said sum output of a respective one of said plurality of adders, each of said plurality of accumulators having an output connected back to said second input of the adder to add said sum data back into said adder;
• a voted data register having a plurality of bit positions, each bit position associated with a respective one of said plurality of adders, each of said bit positions connected to the overflow output of its associated adder and storing said voted data;
• an output gate connected to said voted data register for passing said voted data stored in said voted data register back to said voter memory in response to a recycle signal;
• and
• control logic means responsive to an input signal signifying a particular type of data stored in said voter memory for generating sequence signals identifying the sequence that data from said voter memory is to be loaded into said data register, for generating a load reference number signal enabling said plurality of multiplexers to load said reference number into said plurality of accumulators through said adders, for generating an add signal enabling said multiplexers to pass said data stored in said data registers to said adders to be added to said sum data stored in said accumulators, and for generating said recycle signal when necessary enabling said voted data to be stored in said voter memory.