Application specific integrated circuit

In a system comprising a pair of data handling stations linked by a data transmission path and comprising interrogation and data receiving means at one of said stations, means at the other station comprising:

• register means for serially receiving data from and for serially transmitting data in said register means to, said first station;
• means for storing data received in said register means;
• means for feeding data into said register means for subsequent transmission;
• timing oscillator means for providing timing functions for said second station means and for synchronizing data flow from, and data reception capability at, said first station means;
• said timing means generating a shift clock signal for said register means for stepping said register means synchronously with serially received data from said first station and for stepping said register means synchronously with the data reception capability at said first station;
• validating means detecting presence of start and stop bit data in predetermined locations in said register means defining a data phrase received from said first station;
• means detecting command bit data in said received phrase;
• and
• means responsive to simultaneous output of said validating means and to output of said command bit data detecting means for switching said means for storing data and said means for feeding data in accordance with said command bit data.

In a system comprising a pair of data handling stations linked by a data transmission path and comprising interrogation and data receiving means at a first of said stations, means at the second of said stations comprising:

• register means for receiving serial data from said first station;
• latch means for storing data received in said register means;
• timing oscillator means for providing timing functions for said second station means and for synchronizing data flow from and data reception capability at, said first station;
• said timing means generating a shift clock signal for said register means for stepping said register means synchronously with a data bit stream received from said first station;
• validating means detecting presence of start and stop bit data defining said stream in predetermined locations in said register means;
• means detecting command bit data in said stream;
• means responsive to the output of said validating means and to detected command bit data for switching said latch means for storing data received in said register means;
• and
• output means responsive to said latch means for driving output devices at said second station.

A circuit which comprises,

• a shift register,
• mode control means for said circuit for conditioning said shift register to a plurality of operating states,
• local data generating means,
• a terminal for receipt and transmission of serial data fed thereto,
• storage means for subsequent utilization of data received by said shift register from said terminal,
• said mode control means alternatively conditioning said shift register for receiving serial data from said terminal and for conditioning said shift register for receiving local data from said local data generating means,
• said mode control means also conditioning said shift register for feeding said local data therein serially to said terminal,
• and means responsive to chosen received serial data at said terminal for actuating said mode control means.