Phase locked loop circuit with quickly recoverable stability

A phase locked loop circuit comprising:

• a voltage-controlled oscillator oscillating at a frequency corresponding to a voltage applied thereto;
• a frequency divider for dividing the oscillation frequency of the voltage-controlled oscillator;
• a phase comparator for comparing phases of a reference signal inputted to the PLL circuit and an output signal of the frequency divider;
• a low-pass filter for converting a phase comparison result of the phase comparator to a voltage for controlling the voltage-controlled oscillator;
• first control means responsive to a discontinuous phase change of the reference signal for preventing a phase change of the reference signal from being transmitted through the low-pass filter to the voltage-controlled oscillator during a predetermined period;
• and
• second control means responsive to the discontinuous phase change of the reference signal for forcedly pulling-in the phase of the PLL circuit so that the phase of the output signal of the frequency divider is locked to a new phase of the reference signal after the discontinuous phase change during a predetermined period.