Transistor delay circuits
AssigneeInternational Business Machines Corporation
InventorsAlbert M. Chu, William R. Griffin
Life of this patent
Estimating the term…
Abstract
A signal delay circuit is provided which includes first and second circuits arranged parallel to each other, the first circuit having serially connected first and second transistors and the second circuit having a third transistor, and a fourth transistor connected from the common point between the first and second transistors to the second circuit, a signal is applied to one end of the parallelly arranged first and second circuits while the first, second and fourth transistors are turned on with the third transistor being turned off.
Claims23
A signal delay circuit comprising
- an input terminal,
- an output terminal,
- first and second circuits arranged parallel to each other and disposed between said input and output terminals, said first circuit having serially connected first and second transistors and said second circuit having a third transistor,
- a fourth transistor connected from the common point between said first and second transistors to said second circuit,
- means for applying a signal to said parallelly arranged first and second circuits,
- turning on said first, second and fourth transistors, and means for selectively turning on said third transistor.
A signal delay circuit comprising
- first and second circuits coupled in parallel to each other, said first circuit having serially connected first and second transistors of a given type conductivity and said second circuit having a third transistor of a conductivity type opposite to that of said given type conductivity,
- a fourth transistor connected from the common point between said first and second transistors to said second circuit,
- means for applying a given signal to said first and second circuits, and
- means for applying a signal which is the complement of said given signal to the control electrodes of said transistors.
A signal delay circuit comprising
- first and second circuits connected in parallel with each other, said first circuit including serially connected first and second transistors of a given type conductivity and said second circuit including serially connected third and fourth transistors of a conductivity type opposite to that of said given type conductivity,
- a fifth transistor of said given type conductivity connected from the common point between said first and second transistors to the common point between said third and fourth transistors,
- a sixth transistor of said opposite type conductivity connected from the common point between said first and second transistors to the common point between said third and fourth transistors,
- means for applying a given signal to said parallelly arranged first and second circuits, and
- means for applying a signal which is the complement of said given signal to the control electrodes of said transistors.
A signal delay circuit as set forth in claim wherein the output of said inverter is coupled to said parallelly arranged first and second circuits and the input of said inverter is coupled to the control electrodes of said transistors.
A signal delay circuit comprising
- an input terminal,
- an output terminal,
- a first series circuit including first and second N-channel field effect transistors having a first common node therebetween connected between said input and output terminals,
- a third N-channel field effect transistor having one end thereof including said first common node, said first common node being an N-type conductivity diffusion region forming a P-N junction with a P-type semiconductor substrate,
- a second series circuit including first and second P-channel field effect transistors having a second common node therebetween connected between said input and output terminals,
- a third P-channel field effect transistor having one end thereof including said second common node, said second common node being a P-type conductivity diffusion region forming a P-N junction with an N-type semiconductor substrate,
- means for connecting the other end of said third P-channel transistor to said first common node and for connecting the other end of said third N-channel transistor to said second common node,
- means for applying a given signal to said input terminal, and
- means for applying a signal which is the complement of said given signal to the control electrodes of said transistors.
Dependencies are inferred from the claim text.