US 4,812,684 AGranted

Multiphase clock distribution for VLSI chip

AssigneeHitachi, Ltd.

InventorsAkira Yamagiwa, Toshihiro Okabe

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Abstract

Multi-phase clock signals are delivered to a large number of load circuits scattered on a chip from clock signal input pins through at least three stage buffer circuits. The first stage buffer circuits are arranged in the neighborhood of the input pins, and the second stage buffer circuits are arranged on the central portion of the chip. Equivalent-length wirings are made between the successive two stage buffer circuits and the same number of subsequent stage buffer circuit are connected with each of certain stage buffer circuits for the respective phases so as to provide equal resistances and equal capacitances. Equivalent-length wirings are also made between final stage buffer circuits and the corresponding load circuits, and the same number of load circuits are connected with each final stage buffer circuit. Thus, equal delay times are provided in the clock signal paths from the input pins to the load circuits at the respective phases.

Claims6

Dependent claims

A large scale semiconductor logic device operated by a plurality of clock signals having different phases which is arranged on a chip, comprising:

(A) a plurality of input terminals for receiving said plurality of clock signals;
(B) a plurality of buffer circuits constructed in at least three stages in series connection, which are connected with each of said plurality of input terminals, in which first stage buffer circuits are arranged in the neighborhood of said input terminals and connected therewith and second stage buffer circuits are arranged at the central portion of the chip and connected with said first stage buffer circuits;
and
(C) a plurality of load circuits receiving said plurality of clock signals through said plurality of buffer circuits, said plurality of load circuits being connected with final stage buffer circuits of said plurality of buffer circuits;
between said second stage buffer circuits and said final stage buffer circuits, wirings are made between the buffer circuits belonging to successive stages so that the path lengths therebetween are substantially equal and each of certain stage buffer circuits is connected with the same number of subsequent stage buffer circuits;
and wirings are made between the final stage buffer circuits and the load circuits so that the path lengths therebetween are substantially equal and each of the final stage buffer circuits is connected with the same number of load circuits.

3 more elements

Dependencies are inferred from the claim text.