Merged CCD/MOS integrated circuit
AssigneeHughes Aircraft Company
InventorJames G. Nash
Life of this patent
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Abstract
A digital integrated circuit that includes on a common substrate both charge-coupled device (CCD) circuitry and metal-oxide semiconductor (MOS) circuitry that combine together efficiently to implement a complex digital function such as a multi-bit multiplier or divider. The CCD circuitry includes an array of full adder cells and the MOS circuitry selectively processes and channels certain bits of a plurality of digital input bits to the individual full adder cells, such processing being based on other of the digital input bits. The introduction of MOS logic into the CCD circuit permits greater flexibility in the layout and interconnection of the individual full adder cells and permits the utilization of more efficient algorithms than otherwise could be used in circuits having CCD elements alone.
Claims8
An integrated circuit for providing multi-bit parallel multiplication or
- multi-bit parallel division, comprising:
- a substrate;
- digital input means located on the substrate for receiving a plurality of digital input bits to be processed by the integrated circuit;
- charge-coupled device means located on the substrate and including a plurality of full adder cells arranged in a two-dimensional array of sequential stages, with sum and carry output bits from each stage being channel to predetermined full adder cells of the next sequential stage, if any;
- metal-oxide semiconductor means located on the substrate for selectively channeling certain of the digital input bits to multiple stages of the two-dimensional array of full adder cells in accordance with other of the digital input bits;
- and
- digital output means located on the substrate for outputting a plurality of digital output bits produced by the plurality of full adder cells.
A parallel radix-4 digital multiplier integrated circuit comprising:
- a substrate;
- digital input means located on the substrate for receiving a multi-bit multiplier and a multi-bit multiplicand to be multiplier together by the integrated circuit;
- a sequential array of charge-coupled device full adder stages located on the substrate, each stage transferring sum and carry bits to the next succeeding stage;
- metal-oxide semiconductor recoder means located on the substrate for processing the multi-bit multiplier and generating a plurality of control signals based thereon;
- metal-oxide semiconductor selector means, located on the substrate and responsive to the control signals and to the multi-bit multiplicand, for channeling selected bits of the multiplicand to multiple stages of the array of full adder stages;
- wherein the full adder stages operate on the selected bits channeled to them and the sum and carry its transferred between successive stages, to produce a multi-bit product;
- digital means located on the substrate for outputting the multi-bit product produced by the array of full adder stages;
- and
- wherein the array of full adder stages is arranged such that none of the charge paths interconnecting the individual full adder stage cross over each other.
Dependencies are inferred from the claim text.