Bit slice multiplication circuit

A multiplication circuit comprising:

• a first register for holding a multiplier having a length of 2m-by-n bits;
• first means for sequentially outputting n sets of 2m bits of the multiplier from said first register, one set at one time;
• decoder means for decoding a set of bits taken out by said first means;
• a second register for holding a multiplicand having a length 2m-by-n bits, said second register including shift means operating to shift the bit position of the multiplicand by 2m-bits in the ascending direction of bit position cyclically to produce a 2m-bit output for each multiplying operation by each ultiplier set;
• n multiplying units, each corresponding to one of the n sets of 2m-bit outputs from said shift means and each implementing multiplication for the 2m-bits of the multiplicand from said shift means and the output of said decoder means;
• n adding units, each corresponding to one of said n multiplying units, each adding unit incuding an adder and registers for holding a sum and carry produced by said addeer, each adding unit adapted for implementing summation for a high-order half bit portion of the output of the corresponding multiplying unit, a low-order half bit portion of the output of the cyclically next higher-order multiplying unit with respect to the corresponding multiplying unit and the contents of said register, with the result of the summation being held in said register, summation for the contents of said register and a low-order half bit portion of a product for a set of bits of the lowest-order portion of the multiplicand, among the multiplication results from multiplying units, and a sequentially taken out multiplier being carried out merely for producing a carry output, separately from summations for high-order half bit portions of the outputs of the cyclically next lower-order multiplying units;
• and
• summing means for summing respectively sums and carries held in the registers of said adding units produced as a result of summations for all multiplication results, and outputting the result of the multiplying operation.