Multinode reconfigurable pipeline computer

A reconfigurable computer apparatus comprising:

• a first group of programmable processors permanently connected together in a first configuration having four (4) inputs and one (1) output, said first group including a first programmable processor having at least two (2) inputs and at least one (1) output;
• a second programmable processor having at least two (2) inputs and at least one (1) output;
• and, a third programmable processor having two (2) inputs permanently connected to the outputs of said first and second programmable processors, said third programmable processor also having an output, such that the four inputs of said first group comprise the inputs of said first and second programmable processors and the output of said first group comprises the output of said third programmable processor;
• a second group of programmable processors permanently connected together in a second configuration different from said first configuration, said second group having three (3) inputs and one 91) output and including a fourth programmable processor having two (2) inputs and one (1) output;
• and, a fifth programmable processor having two (2) input and one (1) output, one of said inputs of said fifth programmable processor being permanently connected to the output of said fourth programmable processor, such that the three (3) inputs of said second group comprise the two (2) inputs to said fourth programmable processor and the input to said fifth programmable processor not connected to the output of said fourth programmable processor, and the output of said second group comprising the output of said fifth programmable processor;
• a third group or programmable processors comprising individual processors having two (2) inputs and one (1) output;
• switching means (FLONET) for selectively connecting said first, second and third groups together;
• and,
• sequencer means for providing instructions to said FLONET once a clock cycle,
• wherein said apparatus selectively performs different computations according to instructions from said sequencer means once a clock cycle.

A reconfigurable computer apparatus including arithmetic/logic units (ALU), said apparatus comprising:

• at least a first substructure including three (3) ALU units permanently connected together in a first configuration having four (4) inputs and one (1) output;
• at least a second substructure including two (2) ALU units permanently connected together in a second configuration having three (3) inputs and one (1) output;
• at least a third substructure including at least one individual ALU unit having two (2) outputs and one (1) output;
• switching means for selectively connecting said first, second and third substructure together;
• and,
• sequencer means for providing instructions to said switching means,
• wherein said apparatus selectively performs computations according to instructions from said sequencer means.

A node apparatus for use in a multi-node, parallel processing system, said node apparatus comprising:

• an internal memory including a plurality of memory planes;
• a dynamically reconfigurable arithmetic logic (ALU) pipeline means for performing computations, including a plurality of ALUs at least three of which are permanently connected to each other;
• an ALU pipeline configuration switching network means (FLONET) for selectively connecting groups of said ALUs in said dynamically reconfigurable arithmetic logic pipeline means together;
• a memory/ALU/switch network (dASNET) for transferring data from the memory planes of said internal memory through said MASNET to said dynamically reconfigurable ALU pipeline means and from said dynamically reconfigurable ALU pipeline means through said MASNET to said internal memory;
• and,
• sequencer means for providing instructions to said FLONET,
• wherein said dynamically reconfigurable ALU pipeline means selectively performs different computations according to instructions from said sequencer means.

The apparatus of claim 29 wherein said first group of programmable processors comprises:

• a first programmable processor having at least two (2) inputs and at least one (1) output;
• a second programmable processor having at least two (2) inputs and at least one (1) output;
• and,
• a third programmable processor having two (2) inputs permanently connected to the outputs of said first and said second programmable processors, said third programmable processor also having an output,
• wherein the inputs to said first group comprise the inputs of said first and second programmable processors and the output of said first group comprises the output of said third programmable processor.