Sample-and-hold phase detector circuit
AssigneeHughes Aircraft Company
InventorJames A. Crawford
Life of this patent
Estimating the term…
Abstract
A sample-and-hold phase detector (30, 80, 90, 100, 110) which includes sample-and-hold circuitry (FIG. 6) having variable efficiency. Specifically, the sample-and-hold circuitry provides a sampling pulse of variable width which is controlled to be wider during acquisition and narrower during steady-state operation. Also provided is protection circuitry to neutralize leakage of the input signal to the output of the circuit when a sample control signal is not present.
Claims8
A sample-and-hold circuit responsive to a sample control signal for sampling an input signal provided by a signal generator, which has a characteristic resistance, during a sample interval of controllable duration, comprising:
- a hold capacitor having a capacitance value selected in regard to the value of said signal generator characteristic resistance such that the RC time constant resulting therefrom is less than the duration of the selected sample interval;
- sample pulse means for defining the sample interval by providing a sample pulse controllably having a first duration or a second duration which is greater than said first duration, comprising:
- a step recovery diode having a depletion time dependent upon its level of bias;
- bias means for providing bias current to said step recovery diode and for controlling the level of said bias current to control the duration of said sample pulse and to effect switching of said step recovery diode between on and off states in response to said sample control signal;
- and
- pulse means responsive to the switching of said step recovery diode for generating said sample pulse of variable duration;
- switching means responsive to said sample pulse of variable duration for providing a low impedance coupling of said input signal to said hold capacitor during the presence of said sample pulse, and for providing a high impedance coupling of the input signal to said hold capacitor in the absence of said sample pulse.
A sample-and-hold circuit responsive to a sample control signal for sampling an input signal provided by a signal generator, which has a characteristic resistance, during a sample interval of controllable duration, comprising:
- a hold capaciator having a capacitance value selected in regard to the value of said signal generator characteristic resistance such that the RC time constant resulting therefrom is less than the duration of the selected sample interval;
- sample pulse means for defining the sample interval by providing a sample pulse controllably having a first duration or a second duration which is greater than said first duration;
- switching means responsive to said sample pulse of variable duration for providing a low impedance coupling of said input signal to said hold capacitor during the presence of said sample pulse, and for providing a high impedance coupling of the input signal to said hold capacitor in the absence of said sample pulse;
- and
- neutralizing means coupled to said hold capacitor and responsive to said input signal for neutralizing leakage current perturbations on said hold capacitor.
A sample-and-hold circuit for sampling an input signal comprising:
- sample pulse means responsive to a sample control signal for providing a sampling pulse;
- pulse width control means for selectively controlling the width of said sampling pulse, comprising:
- a diode having a stored charge depletion time dependent upon bias level;
- and
- bias means for providing bias current to said diode and for controlling the level of said bias current to control the width of said sample pulse;
- wherein said sample pulse means comprises pulse means for selectively depleting the stored charge of said diode in response to the sample control signal;
- switching means responsive to the input signal and said sampling pulse for providing a sampled signal as a function of the input voltage during the presence of said sampling pulse;
- and
- storage means for storing said sampled signal.
Dependencies are inferred from the claim text.