Instruction issuing mechanism for processors with multiple functional units
AssigneeCornell Research Foundation, Inc.
InventorHwa C. Torng
Life of this patent
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Abstract
An instruction issuing mechanism for boosting throughput of processors with multiple functional units. A Dispatch Stack (DS) and a Precedence Count Memory (PCM) are employed which allow multiple instructions to be issued per machine cycle. Additionally, instructions do no have to be issued according to their order in the instruction stream, so that non-sequential instruction issuance occurs. In this system, multiple instruction issuance and non-sequential instruction issuance policies enhance the throughput of processors with multiple functional units.
Claims19
An instruction issuing system for a processor including an execution unit having multiple functional units comprising:
- an instruction issuing unit receiving instructions from a memory, operating on instructions and forwarding instructions to said execution unit, said instruction issuing unit including means for detecting the existence of concurrencies in said instructions received from said memory;
- and
- said instruction issuing unit further including means for issuing multiple instructions and non-sequential instructions to said execution unit within a single processor cycle when a concurrency is detected by said means for detecting the existence of concurrencies in said instructions.
A method of issuing instructions for a processor having multiple functional units comprising the steps of:
- reading in and storing instructions from an instruction stream into a dispatch stack, said instructions having an instruction formate of OP, S1, S2, D, where:
- OP is the arithmetic/logic operation to be performed;
- S1 is the register which provides the first of two or the only operand called for;
- S2 is the register yielding the second operand, and
- D is the register receiving the result of the arithmetic/logic operation;
- detecting the existence of concurrencies in instructions stored in said dispatch stack and;
- issuing multiple instructions and non-sequential instructions within a given processor cycle when the existence of concurrencies is detected.
An instruction issuing system for a processor including an execution unit having multiple functional units comprising:
- an instruction issuing unit receiving instructions from a memory, said instruction issuing unit operating on instructions and forwarding instructions to said execution unit, said instruction issuing unit including means for detecting the existence of a plurality of instructions received from said memory which are concurrently executable;
- and
- said instruction issuing unit further including means for issuing multiple instructions and non-sequential instructions to said execution unit within a single processor cycle when concurrently executable instructions are detected by said means for detecting the existence of concurrently executable instructions in said instructions.
A method of issuing instructions for a processor having an execution unit with multiple functional units comprising the steps of:
- reading in and storing instructions from an instruction stream into a dispatch stack;
- detecting the existence of plurality of instructions which are concurrently executable from those instructions stored in said dispatch stack;
- and
- issuing multiple instructions and non-sequential instructions within a given processor cycle when said plurality of concurrently executable instructions are detected.
Dependencies are inferred from the claim text.