Active load for emitter coupled logic gate
AssigneeMotorola, Inc.
InventorsThomas P. Bushey, Bor-Yuan Hwang
Life of this patent
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Abstract
An active load for a CML or ECL logic gate for substantially increasing the speed of the gate comprises a transistor having its base coupled to its collector by a first resistor, and its collector-emitter path coupled in series with a second resistor. This load provides an inductive impedance when the small signal emitter resistance is less than the sum of the resistance of the base and the first resistor, causing a peaking effect resulting in high switching speed.
Claims11
An improved logic gate having first and second voltage terminals, first and second input terminals, a first output terminal, a first current source, a first transistor having a base coupled to said first input terminal, an emitter coupled to said first voltage terminal by said first current source, and a collector coupled to said first output terminal, and a second transistor having a base coupled to said second input terminal, an emitter coupled to said first voltage terminal by said first current source, and having a collector, said improvement comprising:
- a first resistor;
- a second resistor;
- a third resistor;
- a fourth resistor;
- a third transistor having its base coupled to its collector by said first resistor, and its collector-emitter path coupled in series with said second resistor between said collector of said first transistor and said second voltage terminal;
- and
- a fourth transistor having its base coupled to its collector by said third resistor, and its collector-emitter path coupled in series with said fourth resistor between said collector of said second transistor and said second voltage terminal.
A logic gate comprising:
- a first supply voltage terminal;
- a second supply voltage terminal;
- a first input terminal;
- a second input terminal;
- a first output terminal;
- a first current source;
- a first resistor;
- a second resistor;
- a third resistor;
- a fourth resistor;
- a first transistor having a base coupled to said first input terminal, an emitter coupled to said second supply voltage terminal by said first current source, and a collector to said first output terminal;
- a second transistor having a base coupled to said second input terminal, an emitter coupled to said second supply voltage terminal by said first current source, and a collector;
- a third transistor having its base coupled to its collector by said first resistor, and its collector-emitter current path coupled in series with said second resistor between said collector of said first transistor and said first supply voltage terminal;
- and
- a fourth transistor having its base coupled to its collector by said third resistor, and its collector-emitter current path coupled in series with said fourth resistor between said collector of said second transistor and said first supply voltage terminal.
An logic gate comprising:
- a first supply voltage terminal;
- a second supply voltage terminal;
- a first input terminal;
- a second input terminal;
- a first output terminal;
- a first current source;
- a first resistor;
- a second resistor;
- a first transistor having a base coupled to said first input terminal, an emitter coupled to said second supply voltage terminal by said first current source, and a collector;
- a second transistor having a base coupled to said second input terminal, an emitter coupled to said second supply voltage terminal by said first current source, and a collector;
- a third transistor having its base coupled to its collector by said first resistor, and its collector-emitter current path coupled in series with said second resistor between said collector of said first transistor and said second supply voltage terminal;
- and
- first means coupled between said collector of said first transistor and said first output terminal for amplifying the voltage on said collector of said first transistor.
Dependencies are inferred from the claim text.