Method and apparatus for pulse code modulation combination chip having an improved autozero circuit

Apparatus for correcting an off-set signal combined with an input signal, said apparatus comprising:

• (a) sign means for determining a sign of a combined input signal applied thereto, said sign means comprising an analog-to-digital converter, said combined input signal comprising said input signal, said off-set signal and an analog signal;
• (b) storage means for changing a value stored therein in response to said sign means when said input signal is absent from said combined input signal, said storage means including comparison means for comparing an incoming sign signal with a sign signal from a previous period, wherein said comparison means provides for updating of said storage means value after said comparison means has compared said incoming sign signal and said sign signal from a previous period as having equivalent signs a predetermined number of times, said storage means comprises an up-down counter for storing said value;
• and
• (c) conversion means for providing said analog signal in response to said storage means value, said analog signal being combined with said input signal and said off-set signal.

Apparatus for providing a pulse code modulated output signal that is an accurate representation of a band pass analog input signal comprising:

• (a) an analog-to-digital converter coupled to said band pass analog input signal, said analog-to-digital converter generating consecutive sign output signals comprising constant sign output signals corresponding to the absence of said band pass analog input signal and consecutive and variable sign output signals corresponding to the presence of said band pass analog input signal;
• (b) counter means coupled to said analog-to-digital converter for receiving said consecutive sign output signals from said analog-to-digital converter, said consecutive sign output signals being a first input signal into said counter means;
• (c) circuit means also coupled to said analog-to-digital converter for receiving, storing, and comparing signs of said consecutive sign output signals from said analog-to-digital converter, said circuit means being designed to generate a second input signal for said counter means, said second input signal for said counter means comprising:
• (i) an enabling input signal for said counter means upon said circuit means detecting that said consecutive sign output signals from said analog-to-digital converter have occured constantly without sign change for a set number of periods, and
• (ii) a disabling input signal for said counter means upon said circuit means detecting a change in sign of said consecutive sign output signals from said analog-to-digital converter,
• said enabling input signal causing said counter means to restart and update contents and said disabling input signal not affecting contents of said counter means,
• said enabling input signal continuously updating said contents of said counter means during an initialization phase when said band pass analog input signal is not present and thus causing said counter means to continuously store an analog correction signal representation of an offset voltage;
• and
• (d) digital-to-analog converter means coupled to said counter means for applying said analog correction signal contained in said counter means to said analog-to-digital converter, said applying of said analog correction signal occuring continuously during presence of said band pass analog input signal, said disabling input signal being continuously generated during a normal operation phase when said band pass analog input signal is present, said counter means maintaining contents from said initialization phase during said normal operation phase and thereby providing a modulated pulse code that is an accurate representation of a band pass analog input signal.