Modulo address generator

Apparatus for generating an address for accessing a target location in a circular buffer of length L, such address being termed a target address, the buffer having an upper address boundary and a lower boundary, the lower boundary being at an address which is a multiple of an integer power of two, and the target address of the target location being offset by M locations from a current buffer address A, where the offset M is no larger than the buffer length L, such apparatus comprising:

• a. means for forming an absolute address equal to the current buffer address A plus the offset M;
• b. means for forming a wrapped address equal to the absolute address less the length of the buffer when the absolute address exceeds the upper address boundary of the buffer and for forming a wrapped address equal to the absolute address pulse the length of the buffer when the absolute address is less than the lower address boundary of the buffer;
• and
• c. means for selecting as the target address the absolute address when the absolute address is neither less than the buffer's lower address boundary nor greater than the buffer's upper address boundary, for selecting as the target address the wrapped address when the absolute address is outside one of the buffer address boundaries.

Apparatus for generating an address for accessing a target location in a circular buffer of length L, such address being termed a target address, the buffer having an upper address boundary and a lower address boundary, the lower address boundary being an address which is a multiple of an integer power of 2, and the target address of the target location being offset by M locations from a current buffer address A, where M is no larger than L, such apparatus comprising:

• a. means for providing a summation of the current buffer address and the offset M, as an absolute address;
• b. means for providing a first wrapped address equal to the sum of the absolute address and the length of the buffer;
• c. means for providing a second wrapped address equal to a difference formed by subtracting from the absolute address an amount equal to the length of the buffer;
• and
• d. means for selecting as the target address one from among the group containing (i) the absolute addresses, (ii) the first wrapped address and (iii) the second wrapped address.

Apparatus for generating an address for accessing a target location in a circular buffer of length L, such address being termed a target address, the buffer having an upper address boundary and a lower address boundary, the lower address boundary being an address which is a multiple of an integer power of 2, and the target address being offset by M locations from a current buffer address A, where M is no larger than L and includes a sign bit indicating the direction of the offset from the current buffer address A, such apparatus comprising:

• a. a register holding a binary word representing the length of the buffer, such register being termed the L register.
• b. a ripple-carry adder for generating a summation of the current buffer address A and the offset M, said summation being termed an absolute address;
• c. means for providing as a direction control signal, the sign bit of the offset M;
• d. an adder/subtractor which provides a wrapped address by adding the summation from the ripple-carry adder to the binary word in the L register in response to a direction control signal being provided in a first state and by subtracting the binary word in the L register from the summation from the ripple-carry adder in response to the direction control signal being provided in a second state;
• e. the adder/subtractor also outputting on a separate set of lines, the carry bit corresponding to each sum bit;
• f. means for selecting as a first boundary-crossing signal the carry bit from the ripple-carry adder which is from the same bit position as the most significant one (i.e., 1) in the binary word in the L register;
• g. means for selecting as a second boundary-crossing signal the carry bit from the adder/subtractor which is from the same bit position as the most significant one (i.e., 1) in the binary word in the L register;
• h. means responsive to the direction control signal for generating a wrap control signal by inverting the first boundary-crossing signal when the direction control signal is in a first state and logical-ORing the first and second boundary-crossing signals a when the direction control signal is in a second state;
• and
• i. means responsive to the wrap control signal for selecting as the target address the absolute address when the wrap control signal is in a first state and for selecting as the target address the wrapped address when the wrap control signal is in a second state.