Time delay circuit for a semiconductor device

A semiconductor device comprising:

• a plurality of delay circuits delaying an input signal having a first level and a second level, said delay circuits having a predetermined delay time;
• a selection circuit connected to said delay circuits, said selection circuit selecting one of said delay circuits, in sequence, in response to a transition from the first level, which is an initial state, to the second level of the input signal and supplying said input signal of said second level to said selected one of said delay circuts, said selection circuit resetting unselected ones of said delay circuits to an initial state;
• a plurality of first gate circuits each of which having input terminals, a first input terminal being connected to an associated one of said delay circuits and a second input terminal being connected to said selection circuit's output terminal associated with said delay circuit, each of said first gate circuits outputting a delayed input signal only from said associated selected one of said delay circuits and inhibiting output from said each associated unselected one of said delay circuits by having a level of said second input terminal of said first gate circuit vary from said second level to said first level;
• and
• a second gate circuit, each input terminal of which being connected to an output terminal of each of said first gate circuits, wherein an output signal from any of said first gate circuits is output from said second gate, a noise pulse having said second level and ending within an interval prior to a a following signal pulse, said interval being essentially shorter than said delay time of said delay circuit, said noise pulse input into one of said delay circuits being inhibited from being output through said associated first gate circuit, and said following signal pulse, of said second level input into another one of delay circuits earlier than said interval which is prior to a next incoming signal pulse, being allowed to be output through said associated first and second gate circuits.