TTL compatible output buffer
AssigneeGazelle Microcircuits, Inc.
InventorsAndrew C. Graham, Mark E. Fitzpatrick
Life of this patent
Estimating the term…
Abstract
This invention discloses a TTL compatible output buffer circuit which provides that in the state where the output signal thereof is high, no substantial current is provided inward of the buffer circuit from the output signal lead over a wide range of voltages applied to the output signal lead, including applied voltages substantially greater than that supplied by the voltage supply terminals of the circuit, with the circuit being further implemented in compound semiconductor technology.
Claims16
A buffer circuit having a buffer circuit input signal lead for receiving an input signal, a buffer circuit output signal lead for providing an output signal, a first voltage supply terminal and a second voltage supply terminal, comprising means for providing that in the state with the output signal high, no substantial current is provided inward of the buffer circuit from the output signal lead over a wide range of voltages applied to the output signal lead, including applied voltages substantially greater than that receivable by the first and second voltage supply terminals, and wherein said buffer circuit is implemented in compound semiconductor technology.
A buffer circuit having first and second input signal leads for receiving input signals, a buffer circuit output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising:
- a first transistor having a first current handling terminal connected to the first voltage supply terminal, a control terminal connected to the first input signal lead, and a second current handling terminal;
- load means connected to the second current handling terminal of the first transistor;
- a second transistor having a first current handling terminal connected to the load means, a control terminal connected to the second input signal lead, and a second current handling terminal connected to the second voltage supply terminal;
- said output signal lead connected to the first current handling terminal of the second transistor;
- wherein said circuit is implemented in compound semiconductor technology.
A buffer circuit having first and second buffer circuit input signal leads for receiving input signals, a buffer circuit output signal lead for providing an output signal, a first voltage supply terminal and a second voltage supply terminal, comprising:
- a first transistor having a first current handling terminal connected to the first voltage supply terminal, a control terminal connected to the first input signal lead, and a second current handling terminal connected to the second voltage supply terminal;
- a second transistor having a first current handling terminal connected to the first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal;
- a third transistor having a first current handling terminal connected to the second current handling terminal of the second transistor, a control terminal connected to the first input signal lead, and a second current handling terminal connected to the second voltage supply terminal;
- load means connected to the first voltage supply terminal;
- a fourth transistor having a first current handling terminal connected to the load means, a control terminal connected to the second input signal lead, and a second current handling terminal;
- a diode connected to the second current handling terminal of the fourth transistor, and connected to the output signal lead, and forward biased in the direction from the first voltage supply terminal to the output signal lead;
- a fifth transistor having a first current handling terminal connected to the output signal lead, a control
- connected to the first current handling terminal
- of the third transistor, and a second current terminal handling terminal connected to the second voltage supply terminal
Dependencies are inferred from the claim text.