Slow reproducing apparatus for VTR or VCR using image memory

A slow reproducing apparatus for VTR/VCR using an image memory comprising:

• signal generating means for generating a write timing signal in accordance with a reproduced control signal from a video tape;
• image memory means for storing video signal data of a reproduced video signal from said video tape in accordance with said write timing signal and a given address clear signal which designates write and read start addresses of said image memory means;
• and
• address clear means for detecting a timing difference between a write timing and a read timing in said image memory means when slow reproduction is performed and correcting address clear signal generation timing so that the amount of said timing difference is substantailly minimized, said address clear means including:
• phase difference detecting means for providing phase difference data indicating a difference between a write phase and a read phase of said video signal data in said image memory means,
• counter means for providing count data indicating how many fields of video signal data are read out from said image memory means since said write timing signal has been generated, said count data being updated in accordance with a slow rate indicating a ratio of a tape running speed during slow reproducing to a standard tape running speed, and
• timing updating means for updating a reference address clear pulse generation timing of a reference address clear pulse based on a ratio of the phase difference data to the pulse based on a ratio of the phase difference data to the count data, and providing given address clear pulse.

A slow reproducing apparatus for VTR/VCR using an image memory comprising:

• signal generating means for generating a write timing signal in accordance with a reproduced control signal from a video tape;
• image memory means for storing video signal data of a reproduced video signal from said video tape in accordance with said write timing signal and a given address clear signal which designates write and read start addresses of said image memory means;
• and
• address clear means for detecting a timing difference between a write timing and a read timing in said image memory means when slow reproduction is performed and corrceting address clear signal generation timing so that the amount of said timing difference is substantially minimized, said address clear means including:
• phase difference detecting means for providing phase difference data indicating a difference between a write phase and a read phase of said video signal data in said image memory means,
• comparing means for comparing the phase difference data with given comparison data, and providing correction data having a content for reducing the difference of the write/read timing only when the content of the phase difference data falls within a range determined by the comparison data, and
• timing updating means for updating a reference address clear pulse generation timing of reference address clear pulse in accordance with the correction data, and providing the given address clear pulse.

A slow reproducing apparatus for VTR/VCR using an image memory comprising:

• signal generating means for generating a write timing signal in accordance with a reproduced control signal from a video tape;
• image memory means for storing video signal data of a reproduced video signal from said video tape in accordance with said write timing signal and a given address clear signal which designates write and read start addresses of said image memory means, said image memory means including:
• first converting means for converting the video signal data into write data in accordance with a given clock signal,
• address counter menas, which is cleared by the address clear signal, for counting the given clock signal to generate address data,
• a read/write memory for storing the write data at an address specified by the address data in a write mode, and outputting read data corresponding o the write data from an address specified by the address data in a read mode,
• second converting means for converting the write data into reproduced video data in accordance with the given clock signal in the write mode, and converting the read data into the reproduced video data in the read mode, and
• third converting means for converting the reproduced video data into an analog composite video signal, and
• address clear means for detecting a timing difference between a write timing and a read timing in said image memory means when slow reporduction is performed and correcting address clear signal generation timing so that the amount of said timing difference is substantially minimized.

A slow reproducing apparatus for VTR/VCR using an image memory comprising:

• signal generating means for generating a write timing signal in accordance with a reproduced control signal from a video tape;
• image memory means for storing video signal data of a reproduced video signal from said video tape in accordance with said write timing signal and an address clear signal which designates write and read start addresses of said image memory means;
• address clear means for detecting a timing difference between a write timing and a read timing in said image memory means when slow reproduction is performed and correcting generation timing so that the amount of said timing difference is substantially minimized, said address clear means including:
• phase adjusting means for adjusting, during the free running period, the phase of a reference address clear pulse, which is independent of a variation in time base of the reproduced video signal, so that the difference between the write and read timings is reduced, and generating the given address clear signal.

A slow reproducing apparatus for VTR/VCR using an image memory comprising:

• signal generating means for generating a write timing signal in accordance with a reproduced control signal from a video tape, said signal generating means including:
• delay means for delaying the reproduced control signal by a predetermined time to generate a delayed signal, and
• synchronization means for converting the delayed signal to the write timing signal in accordance with a synchronization pulse which corresponds to a change in the field of the reproduced video signal in the synchronization period;
• image memory means for storing video signal data of a reproduced video signal from said video tape in accordance with said write timing signal and a given address clear signal which designates write and read start addresses of said image memory means;
• address clear menas for detecting a timing difference between a write timing and a read timing in said image memory means when slow reproduction is performed and correcting address clear signal generation timing so that the amount of said timing difference is substantially minimized;
• and
• intermittent running control means for moving said video tape a predetermined number of fields during a free running period which is defined as a former half period of the write timing signal, and stoppong said video tape during a synchronization period which is defined as a latter half period of the writ timing signal.

A slow reproducing apparatus for VTR/VCR, comprising:

• an A/D converter for converting a video signal reproduced from a magnetic tape to a digital signal;
• means for writing the output from said A/D converter into a field memory;
• means for reading out a digital signal from said memory;
• a D/A converter for converting the digital signal read out from said memory to an analog signal;
• means for correcting a timing error between the read signal and the write signal for said memory;
• and
• intermittent driving means for intermittently driving said magnetic tape, wherein said magnetic tape is intermittently driven during slow reproduction, the output from said A/D converter is written in said memory in a stop state of said tape during the intermittent driving period, and the write signal is read out from said memory in the tape moving state during the intermittent driving period so that a reproduced signal is provided.