Counter circuit with mislatching prevention

Abstract

A counter circuit for counting pulses inputted thereto asynchronously during a fixed period includes a counter 12' for counting the input pulses, a register 13 for storing pulses outputted by the counter 12' at fixed periods, and a control circuit 11' for generating a signal that controls the operating state of the counter 12' and register 13. When a signal that decides the operating period of the counter 12' is not being generated, namely between pulses indicative of the operating period, the counter 12' performs an ordinary counting operation. If an input pulse for counting is applied to the counter 12' during a period of time in which the abovementioned pulse is being generated, the control circuit 11' causes the counting operation to continue without clearing the counted value in the counter 12', after which the counted value in counter 12' is outputted to the register 13 to be latched therein, thereby preventing miscounting in the register 13.

Dependencies are inferred from the claim text.