US 4,794,593 AGranted

Time-division multiplexed communication apparatus

AssigneeGTE Laboratories Incorporated

InventorJoseph M. Lenart

Life of this patent

Estimating the term…

Abstract

Communication system of a plurality of switching nodes connected in a closed ring. A switching stage at each node transmits words of data from node-to-node in a time-division multiplexed data stream. Data can be inserted onto the ring by each switching stage, and data addressed to a switching stage is removed form the ring by that switching stage. Data words are loaded into input registers at each switching stage on the leading edge of a clock pulse, and decoding occurs within each switching stage during the clock pulse. A received word may be transmitted to a succeeding switching stage, or may be removed form the ring and stored in an output register on termination of a clock pulse.

Claims7

Dependent claims

Time-division multiplexed switching apparatus including a plurality of substantially identical switching stages arranged in a closed ring with ring bus means connecting each switching stage to the preceding switching stage of the ring and to the succeeding switching stage of the ring, each switching stage being designated by a unique address, and words of digitally encoded information being transmitted from one switching stage to the succeeding switching stage at a first data rate;

and including means for producing first data rate clock signals at said first data rate coupled to each of said switching stages of the plurality;
each switching stage comprising
a ring input storage means coupled to the ring bus means for receiving and storing a word of digitally encoded information transmitted over the ring bus means from the preceding switching stage, the ring input storage means having an input coupled to the ring bus means from the preceding switching stage and having an output;
a transfer input storage means for receiving and storing a word of digitally encoded information to be transferred onto the ring, said transfer input storage means having an input coupled to a transfer input bus and having an output;
a transfer output storage means for storing a word of digitally encoded information, said transfer output storage means having an input and an output;
multiplexing means having a first input coupled to the output of the ring input storage means, a second input coupled to the output of the transfer input storage means, and an output coupled to the ring bus means to the succeeding switching stage;
said ring input storage means being operable to store a word received on the ring bus means from the preceding switching stage on the leading edge of each first data rate clock signal;
address means for determining if a word stored in the ring input storage means is addressed to the address of the switching stage;
control means coupled to said multiplexing means and being operable when a word is stored in the ring input storage means and the address means determines that the stored word is not addressed to the address of the switching stage to cause the multiplexing means to couple the output of the ring input storage means to the ring bus means to the succeeding switching stage;
said control means being operable when a word is stored in the ring input storage means and the address means determines that the stored word is addressed to the address of the switching stage to cause the multiplexing means to couple the output of the ring input storage means to the input of the transfer output storage means;
said control means being operable when a word is stored in the transfer input storage means, unless a word is stored in the ring input storage means and the address means determines that that word is not addressed to the address of the switching stage, to cause the multiplexing means to couple the output of the transfer input storage means to the ring bus means to the succeeding switching stage;
and
said transfer output storage means being operable in response to the termination of a first data rate clock signal to store a word present at its input.

10 more elements

Dependencies are inferred from the claim text.

patentgrep

Loading patent…

Abstract

and including means for producing first data rate clock signals at said first data rate coupled to each of said switching stages of the plurality;
each switching stage comprising
a ring input storage means coupled to the ring bus means for receiving and storing a word of digitally encoded information transmitted over the ring bus means from the preceding switching stage, the ring input storage means having an input coupled to the ring bus means from the preceding switching stage and having an output;
a transfer input storage means for receiving and storing a word of digitally encoded information to be transferred onto the ring, said transfer input storage means having an input coupled to a transfer input bus and having an output;
a transfer output storage means for storing a word of digitally encoded information, said transfer output storage means having an input and an output;
multiplexing means having a first input coupled to the output of the ring input storage means, a second input coupled to the output of the transfer input storage means, and an output coupled to the ring bus means to the succeeding switching stage;
said ring input storage means being operable to store a word received on the ring bus means from the preceding switching stage on the leading edge of each first data rate clock signal;
address means for determining if a word stored in the ring input storage means is addressed to the address of the switching stage;
control means coupled to said multiplexing means and being operable when a word is stored in the ring input storage means and the address means determines that the stored word is not addressed to the address of the switching stage to cause the multiplexing means to couple the output of the ring input storage means to the ring bus means to the succeeding switching stage;
said control means being operable when a word is stored in the ring input storage means and the address means determines that the stored word is addressed to the address of the switching stage to cause the multiplexing means to couple the output of the ring input storage means to the input of the transfer output storage means;
said control means being operable when a word is stored in the transfer input storage means, unless a word is stored in the ring input storage means and the address means determines that that word is not addressed to the address of the switching stage, to cause the multiplexing means to couple the output of the transfer input storage means to the ring bus means to the succeeding switching stage;
and
said transfer output storage means being operable in response to the termination of a first data rate clock signal to store a word present at its input.

10 more elements