Redundancy circuit for use in a semiconductor memory device

In a semiconductor circuit for substituting a redundant line connected to defect-free redundant memory cells for a normal line connected to defective normal memory cells, wherein the circuit has a normal decoder connected to the normal line, for selecting the normal line identified by a predetermined combination of address signals and their complements, and a redundant decoder connected to the redundant line, for selecting the redundant line in response to the address signals and their complements, said redundant line connected to the normal decoder so as to prevent selection of the normal line upon selection of the redundant line, the redundant decoder comprising:

• a plurality of first address program devices connected in parallel between a reference potential and the redundant line, for connecting or disconnecting the redundant line to the reference potential in response to pairs of input signals formed by each input address signal and the respective complement of each input address signal;
• and
• a second address program device connected in parallel with said first program devices between the reference potential and the redundant line, for connecting or disconnecting the redundant line to the reference potential in response to a pair of signals complementary to a pair of said input signals for one selected device of said plurality of first devices;
• whereby, in a first programmed mode, any one of said one selected first program device and said second program device connects the redundant line to the reference potential so as to deselect the redundant line and select the normal line and, in a second programmed mode accommodating occurrence of defective normal memory cells, each program device disconnects the redundant line to the reference potential so as to select the redundant line.

In a semiconductor circuit for substituting a redundant line coupled to defect-free redundant memory cells for a normal line coupled to defective normal memory cells, wherein said circuit includes address means for providing address signals and their complements, a normal decoder connected between address means and the normal line, for selecting the normal line in response to a predetermined combination of address signals and their complements, and a redundant decoder connected between address means and the redundant line, for selecting the redundant line in response to signals provided by said address means, said redundant decoder connected to the normal decoder to prevent selection of the normal line upon selection of the redundant line, the redundant decoder comprising:

• first address program devices connected in parallel between the redundant line and a reference potential and receiving said address signals and their complements, each first address program device having a programmable element capable of assuming a first address program devices causing respectively connection and disconnection of the redundant line to the reference potential in response to a first logic state and a second logic state of a respective one of said address signals, and the second program state of each of said first address program devices causing respectively connection and disconnection of the redundant line to the ground source in response to the first logic state and the second logic state of a respective one of said complementary address signals;
• and
• a second address program device connected in parallel with said first address program devices between the redundant line and the ground source and receiving input signals which are complementary to those of a selected one of said first address program devices, said second address program device having one said programmable element, the first program state of said second address program device causing respectively connection and disconnection of the redundant line to the reference potential in response to the first logic state and the second logic state of the address signal of said selected one of said first address program devices;
• whereby, all of said first address program devices and said second address program device may be initially programmed in first program state when said normal memory cells are free of defect, wherein any one of said one selected address program devices and said second address program device is connected to the reference potential so as to not select the redundant line, and, each of said first program devices and said second address program device receiving address signals of the first logic state may be programmed in said second program state when said normal memory cells are not free of defect, wherein all of said address program devices are disconnected from the reference potential so as to select the redundant line.

A monolethic integrated semiconductor memory chip, comprising:

• a normal address line connected to a plurality of normal memory cells;
• a redundant address line connected to a plurality of redundant memory cells;
• and
• a redundant address decoder, including:
• a plurality of first address program means coupled in parallel to the redundant address line, for electrically connecting or disconnecting the redundant address line to a reference potential in response to pairs of each input address signal and complement of each input address signal during a first electrical program of said first address program means;
• and
• second address program means connected in parallel with said first address program means to the redundant address line for electrically connecting or disconnecting the redundant address line to a reference potential in response to a pair of signals complementary to a selected one of said pairs of each address signal and complement during a second electrical program of said second address program means.