Nonvolatile semiconductor memory including means for detecting completion of writing operation

A semiconductor memory comprising a plurality of memory transistors each having a control gate, a floating gate, a drain and a source, means response to a set of address signalsffor selecting at least one memory transistor, means for applying a programming voltage between said control gate and said drain of said at least one memory transistor to charge said floating gate thereof at a predetermined value, means coupled to said source of said at least one memory transistor for detecting a potential change at said source caused by a change in a threshold voltage of said at least one memory transistor and thereby producing a detection signal, and means responsive to said detection signal for preventing said programming voltage from being applied to said at least one memory transistor.

A semiconductor memory comprising a plurality of memory transistors each having a control gate, a floating gate, a drain and a source, an address decoder responding to a set of address signals for selecting at least one of said memory transistors, a data writing circuit activated in a data writing mode and supplying a writing voltage between said control gate and said drain of the selected memory transistor, a reference terminal, a source potential control circuit disconnecting said source of said selected memory transistor from said reference terminal in said data writing mode, a source potential detection circuit comparing a potential at said source of said selected memory transistor with a reference voltage and producing an output signal when said potential exceeds said reference voltage, and means responsive to said output signal for inactivating said data write circuit.